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[/] [opencores/] [trunk/] [rts_header.v] - Rev 18
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/////////////////////////////////////////////////////////////////////////////////////////////////// //// //// //// WISHBONE Connection Matrix Top Level //// //// //// //// //// //// Author: B.J. Porcella //// //// bporcella@sbcglobal.net //// //// //// //// //// //// //// /////////////////////////////////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000-2002 B.J. Porcella //// //// Real Time Solutions //// //// //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// /////////////////////////////////////////////////////////////////////////////////////////////////// // CVS Log // // $Id: rts_header.v,v 1.1.1.1 2004-06-18 08:38:39 mihal Exp $ // // $Date: 2004-06-18 08:38:39 $ // $Revision: 1.1.1.1 $ // $Author: mihal $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2004/04/13 23:47:42 bporcella // import first files // // // //-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0 module //-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0 //-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0 //-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0 //-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0 //-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0 //-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0 //-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0 endmodule
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