URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [opencpu32.gise] - Rev 9
Go to most recent revision | Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="opencpu32.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Alu.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Alu.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Alu.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Alu.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Alu.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="Alu.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Alu.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="Alu.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="Alu.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="Alu.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="Alu.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Alu.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Alu.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="Alu.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="Alu.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Alu.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="Alu.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Alu.xst"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="Alu_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_map.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_map_fpga_editor.log"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="Alu_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="Alu_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Alu_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="Alu_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testAlu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
</transform>
<transform xil_pn:end_ts="1332971517" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1332971514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1332971517" xil_pn:in_ck="-3984477231246839023" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7365609629158378897" xil_pn:start_ts="1332971517">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7863675631946613945" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2964161847311656507" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="319318766057190551" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968184" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7168533952405101494" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="Alu.lso"/>
<outfile xil_pn:name="Alu.ngc"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="Alu.prj"/>
<outfile xil_pn:name="Alu.stx"/>
<outfile xil_pn:name="Alu.syr"/>
<outfile xil_pn:name="Alu.xst"/>
<outfile xil_pn:name="Alu_vhdl.prj"/>
<outfile xil_pn:name="Alu_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1332968125" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1210076599156103590" xil_pn:start_ts="1332968125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968131" xil_pn:in_ck="88312569576" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3676465938101052346" xil_pn:start_ts="1332968125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="Alu.bld"/>
<outfile xil_pn:name="Alu.ngd"/>
<outfile xil_pn:name="Alu_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968137" xil_pn:in_ck="88312569577" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1332968131">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.pcf"/>
<outfile xil_pn:name="Alu_map.map"/>
<outfile xil_pn:name="Alu_map.mrp"/>
<outfile xil_pn:name="Alu_map.ncd"/>
<outfile xil_pn:name="Alu_map.ngm"/>
<outfile xil_pn:name="Alu_map.xrpt"/>
<outfile xil_pn:name="Alu_summary.xml"/>
<outfile xil_pn:name="Alu_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968149" xil_pn:in_ck="104733817618758274" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1332968137">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.ncd"/>
<outfile xil_pn:name="Alu.pad"/>
<outfile xil_pn:name="Alu.par"/>
<outfile xil_pn:name="Alu.ptwx"/>
<outfile xil_pn:name="Alu.unroutes"/>
<outfile xil_pn:name="Alu.xpi"/>
<outfile xil_pn:name="Alu_pad.csv"/>
<outfile xil_pn:name="Alu_pad.txt"/>
<outfile xil_pn:name="Alu_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968149" xil_pn:in_ck="88312569445" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1332968146">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.twr"/>
<outfile xil_pn:name="Alu.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
</generated_project>
Go to most recent revision | Compare with Previous | Blame | View Log