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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Rev 207
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#!/bin/bash
#------------------------------------------------------------------------------
# Copyright (C) 2001 Authors
#
# This source file may be used and distributed without restriction provided
# that this copyright statement is not removed from the file and that any
# derivative work contains the original copyright notice and the associated
# disclaimer.
#
# This source file is free software; you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published
# by the Free Software Foundation; either version 2.1 of the License, or
# (at your option) any later version.
#
# This source is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
# License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this source; if not, write to the Free Software Foundation,
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#------------------------------------------------------------------------------
#
# File Name: msp430sim
#
# Author(s):
# - Olivier Girard, olgirard@gmail.com
#
#------------------------------------------------------------------------------
# $Rev: 207 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2015-10-20 22:58:27 +0200 (Tue, 20 Oct 2015) $
#------------------------------------------------------------------------------
###############################################################################
# Parse arguments #
###############################################################################
testname=""
seed=""
dma_verif="DMA_VERIF"
while [[ $# > 0 ]]; do
key="$1"
shift
case $key in
-seed)
seed="$1"
shift
;;
-no_dma)
dma_verif="NO_DMA_VERIF"
;;
*)
testname="$key"
;;
esac
done
###############################################################################
# Parameter Check #
###############################################################################
if [ "$testname" == "" ]; then
echo "ERROR : missing argument"
echo "USAGE : msp430sim <test name> [-seed <seed_nr>] [-no_dma]"
echo "Example : msp430sim c-jump_jge"
echo ""
echo "In order to switch the verilog simulator, the OMSP_SIMULATOR environment"
echo "variable can be set to the following values:"
echo ""
echo " - iverilog : Icarus Verilog (default)"
echo " - cver : CVer"
echo " - verilog : Verilog-XL"
echo " - ncverilog : NC-Verilog"
echo " - vcs : VCS"
echo " - vsim : Modelsim"
echo " - isim : Xilinx simulator"
echo ""
exit 1
fi
# Generate random seed if not specified
if [ "$seed" == "" ]; then
seed=`od -A n -t d -N 4 /dev/urandom`
fi
###############################################################################
# Check if the required files exist #
###############################################################################
asmfile=../src/$testname.s43;
verfile=../src/$testname.v;
incfile=../../../rtl/verilog/openMSP430_defines.v;
linkfile=../bin/template.x;
headfile=../bin/template_defs.asm;
submitfile=../src/submit.f;
if [ "$OMSP_SIMULATOR" == "isim" ]; then
submitfile=../src/submit.prj;
fi
if [ ! -e $asmfile ]; then
echo "Assembler file $asmfile doesn't exist: $asmfile"
exit 1
fi
if [ ! -e $verfile ]; then
echo "Verilog stimulus file $verfile doesn't exist: $verfile"
exit 1
fi
if [ ! -e $submitfile ]; then
echo "Verilog submit file $submitfile doesn't exist: $submitfile"
exit 1
fi
if [ ! -e $linkfile ]; then
echo "Linker definition file template doesn't exist: $linkfile"
exit 1
fi
if [ ! -e $headfile ]; then
echo "Assembler definition file template doesn't exist: $headfile"
exit 1
fi
###############################################################################
# Cleanup #
###############################################################################
echo "Cleanup..."
rm -rf *.vcd
rm -rf *.vpd
rm -rf *.trn
rm -rf *.dsn
rm -rf pmem*
rm -rf stimulus.v
###############################################################################
# Run simulation #
###############################################################################
echo " ======================================================="
echo "| Start simulation: $testname"
echo " ======================================================="
echo ""
echo " Seed: $seed"
echo ""
# Create links
if [[ $(uname -s) == CYGWIN* ]];
then
cp $asmfile pmem.s43
cp $verfile stimulus.v
else
ln -s $asmfile pmem.s43
ln -s $verfile stimulus.v
fi
# Make local copy of the openMSP403 configuration file
# and prepare it for MSPGCC preprocessing
cp $incfile ./pmem.h
sed -ie 's/`ifdef/#ifdef/g' ./pmem.h
sed -ie 's/`else/#else/g' ./pmem.h
sed -ie 's/`endif/#endif/g' ./pmem.h
sed -ie 's/`define/#define/g' ./pmem.h
sed -ie 's/`include/\/\/#include/g' ./pmem.h
sed -ie 's/`//g' ./pmem.h
sed -ie "s/'//g" ./pmem.h
# Use MSPGCC preprocessor to extract the Program, Data
# and Peripheral memory sizes
if command -v msp430-elf-gcc >/dev/null; then
msp430-elf-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
else
msp430-gcc -E -P -x c ../bin/omsp_config.sh > pmem.sh
fi
# Source the extracted configuration file
if [[ $(uname -s) == CYGWIN* ]];
then
dos2unix pmem.sh
fi
source pmem.sh
# Compile assembler code
echo "Compile, link & generate IHEX file (Program Memory: $pmemsize B, Data Memory: $dmemsize B, Peripheral Space: $persize B)..."
../bin/asm2ihex.sh pmem pmem.s43 $linkfile $headfile $pmemsize $dmemsize $persize
# Generate Program memory file
echo "Convert IHEX file to Verilog MEMH format..."
../bin/ihex2mem.tcl -ihex pmem.ihex -out pmem.mem -mem_size $pmemsize
# Start verilog simulation
echo "Start Verilog simulation..."
../bin/rtlsim.sh stimulus.v pmem.mem $submitfile $seed $dma_verif