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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.s43] - Rev 111
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CLOCK MODULE */
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the ACLK and SMCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
/*===========================================================================*/
.global main
.set DMEM_BASE, (__data_start )
.set DMEM_200, (__data_start+0x00)
.set DMEM_250, (__data_start+0x50)
.set BCSCTL1, 0x0057
.set BCSCTL2, 0x0058
WAIT_FUNC:
dec r14
jnz WAIT_FUNC
ret
main:
mov #DMEM_250, r1 ; # Initialize stack pointer
mov #0x0000, &DMEM_200
mov #0x0000, r15
/* -------------- ACLK GENERATION ----------------- */
mov.b #0x00, &BCSCTL1 ; # Div /1
mov #0x0001, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x10, &BCSCTL1 ; # Div /2
mov #0x0002, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x20, &BCSCTL1 ; # Div /4
mov #0x0003, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x30, &BCSCTL1 ; # Div /8
mov #0x0004, r15
mov #0x0130, r14
call #WAIT_FUNC
mov #0x1000, r15
/* -------------- SMCLK GENERATION - LFXT_CLK INPUT ----------------- */
mov.b #0x08, &BCSCTL2 ; # Div /1
mov #0x1001, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x0A, &BCSCTL2 ; # Div /2
mov #0x1002, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x0C, &BCSCTL2 ; # Div /4
mov #0x1003, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x0E, &BCSCTL2 ; # Div /8
mov #0x1004, r15
mov #0x0130, r14
call #WAIT_FUNC
mov #0x2000, r15
/* -------------- SMCLK GENERATION - DCO_CLK INPUT ----------------- */
mov.b #0x00, &BCSCTL2 ; # Div /1
mov #0x2001, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x02, &BCSCTL2 ; # Div /2
mov #0x2002, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x04, &BCSCTL2 ; # Div /4
mov #0x2003, r15
mov #0x0130, r14
call #WAIT_FUNC
mov.b #0x06, &BCSCTL2 ; # Div /8
mov #0x2004, r15
mov #0x0130, r14
call #WAIT_FUNC
mov #0x3000, r15
/* -------------- CPU ENABLE - CPU_EN INPUT ----------------- */
mov #0x0800, r14
call #WAIT_FUNC
mov #0x4000, r15
/* -------------- RD/WR ACCESS TO REGISTERS ----------------- */
mov.b #0x00, &BCSCTL1
mov.b #0x00, &BCSCTL2
mov.b &BCSCTL1, r4
mov.b &BCSCTL2, r5
mov.b #0xff, &BCSCTL1
mov.b &BCSCTL1, r6
mov.b &BCSCTL2, r7
mov.b #0x00, &BCSCTL1
mov.b &BCSCTL1, r8
mov.b &BCSCTL2, r9
mov.b #0xff, &BCSCTL2
mov.b &BCSCTL1, r10
mov.b &BCSCTL2, r11
mov.b #0x00, &BCSCTL2
mov.b &BCSCTL1, r12
mov.b &BCSCTL2, r13
mov #0x5000, r15
mov #0x0010, r14
call #WAIT_FUNC
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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