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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DEBUG INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the debug interface:                                                 */
/*                        - Check Memory RD/WR features.                     */
/*                                                                           */
/*  Note: The burst features are specific to the selected interface          */
/*    (UART/I2C) and are therefore tested in the dbg_uart/dbg_i2c patterns   */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/

.include "pmem_defs.asm"

.global main

        /* ----------------------         SOME VARIABLES IN ROM  --------------- */
diverse_data:
        .word 0x5ab7
        .word 0x6bc8

        /* ----------------------              WAIT FUNCTION     --------------- */
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret

        /* ----------------------                 MAIN           --------------- */
main:
        mov   #0x5a10, &WDTCTL  ; # Disable Watchdog

        mov #DMEM_250, r1       ; # Initialize stack pointer

        mov   #0x1122, &DMEM_210
        mov   #0x3344, &DMEM_212

        mov   #0xaaaa, r5
        mov   #0xbbbb, r6

        mov   #0x2F00, r14
        call  #WAIT_FUNC

        mov   #0x1000, r15


        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff

        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test        ; Interrupt  1                      <unused>
.word end_of_test        ; Interrupt  2                      <unused>
.word end_of_test        ; Interrupt  3                      <unused>
.word end_of_test        ; Interrupt  4                      <unused>
.word end_of_test        ; Interrupt  5                      <unused>
.word end_of_test        ; Interrupt  6                      <unused>
.word end_of_test        ; Interrupt  7                      <unused>
.word end_of_test        ; Interrupt  8                      <unused>
.word end_of_test        ; Interrupt  9                      <unused>
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      <unused>
.word end_of_test        ; Interrupt 12                      <unused>
.word end_of_test        ; Interrupt 13                      <unused>
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET