OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Rev 172

Go to most recent revision | Compare with Previous | Blame | View Log 

/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DIGITAL I/O                                    */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface:                                           */
/*                                   - Read/Write register access.           */
/*                                   - I/O Functionality.                    */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
/*===========================================================================*/

.include "pmem_defs.asm"

.global main

main:
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P1IN          ; P1IN
        mov.b &P1IN,  &DMEM_200
        mov.b #0x55,  &P1IN
        mov.b &P1IN,  &DMEM_201

        mov.b #0xaa,  &P1OUT         ; P1OUT
        mov.b &P1OUT, &DMEM_202
        mov.b #0x55,  &P1OUT
        mov.b &P1OUT, &DMEM_203

        mov.b #0x5a,  &P1DIR         ; P1DIR
        mov.b &P1DIR, &DMEM_204
        mov.b #0xa5,  &P1DIR
        mov.b &P1DIR, &DMEM_205

        mov.b #0x55,  &P1IFG         ; P1IFG
        mov.b &P1IFG, &DMEM_206
        mov.b #0xaa,  &P1IFG
        mov.b &P1IFG, &DMEM_207

        mov.b #0xa5,  &P1IES         ; P1IES
        mov.b &P1IES, &DMEM_208
        mov.b #0x5a,  &P1IES
        mov.b &P1IES, &DMEM_209

        mov.b #0xaa,  &P1IE          ; P1IE
        mov.b &P1IE,  &DMEM_20A
        mov.b #0x55,  &P1IE
        mov.b &P1IE,  &DMEM_20B

        mov.b #0xcd,  &P1SEL         ; P1SEL
        mov.b &P1SEL, &DMEM_20C
        mov.b #0x32,  &P1SEL
        mov.b &P1SEL, &DMEM_20D


        mov.b #0x00,  &P1IN          ; Re-Initialize
        mov.b #0x00,  &P1OUT
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1IFG
        mov.b #0x00,  &P1IES
        mov.b #0x00,  &P1IE
        mov.b #0x00,  &P1SEL

        mov   #0x0001, r15


        /* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P2IN          ; P2IN
        mov.b &P2IN,  &DMEM_210
        mov.b #0x55,  &P2IN
        mov.b &P2IN,  &DMEM_211

        mov.b #0xaa,  &P2OUT         ; P2OUT
        mov.b &P2OUT, &DMEM_212
        mov.b #0x55,  &P2OUT
        mov.b &P2OUT, &DMEM_213

        mov.b #0x5a,  &P2DIR         ; P2DIR
        mov.b &P2DIR, &DMEM_214
        mov.b #0xa5,  &P2DIR
        mov.b &P2DIR, &DMEM_215

        mov.b #0x55,  &P2IFG         ; P2IFG
        mov.b &P2IFG, &DMEM_216
        mov.b #0xaa,  &P2IFG
        mov.b &P2IFG, &DMEM_217

        mov.b #0xa5,  &P2IES         ; P2IES
        mov.b &P2IES, &DMEM_218
        mov.b #0x5a,  &P2IES
        mov.b &P2IES, &DMEM_219

        mov.b #0xaa,  &P2IE          ; P2IE
        mov.b &P2IE,  &DMEM_21A
        mov.b #0x55,  &P2IE
        mov.b &P2IE,  &DMEM_21B

        mov.b #0xcd,  &P2SEL         ; P2SEL
        mov.b &P2SEL, &DMEM_21C
        mov.b #0x32,  &P2SEL
        mov.b &P2SEL, &DMEM_21D

        mov.b #0x00,  &P2IN          ; Re-Initialize
        mov.b #0x00,  &P2OUT
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2IFG
        mov.b #0x00,  &P2IES
        mov.b #0x00,  &P2IE
        mov.b #0x00,  &P2SEL

        mov   #0x0002, r15


        /* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P3IN          ; P3IN
        mov.b &P3IN,  &DMEM_220
        mov.b #0x55,  &P3IN
        mov.b &P3IN,  &DMEM_221

        mov.b #0xaa,  &P3OUT         ; P3OUT
        mov.b &P3OUT, &DMEM_222
        mov.b #0x55,  &P3OUT
        mov.b &P3OUT, &DMEM_223

        mov.b #0x5a,  &P3DIR         ; P3DIR
        mov.b &P3DIR, &DMEM_224
        mov.b #0xa5,  &P3DIR
        mov.b &P3DIR, &DMEM_225

        mov.b #0xcd,  &P3SEL         ; P3SEL
        mov.b &P3SEL, &DMEM_226
        mov.b #0x32,  &P3SEL
        mov.b &P3SEL, &DMEM_227

        mov.b #0x00,  &P3IN          ; Re-Initialize
        mov.b #0x00,  &P3OUT
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL

        mov   #0x0003, r15


        /* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P4IN          ; P4IN
        mov.b &P4IN,  &DMEM_230
        mov.b #0x55,  &P4IN
        mov.b &P4IN,  &DMEM_231

        mov.b #0xaa,  &P4OUT         ; P4OUT
        mov.b &P4OUT, &DMEM_232
        mov.b #0x55,  &P4OUT
        mov.b &P4OUT, &DMEM_233

        mov.b #0x5a,  &P4DIR         ; P4DIR
        mov.b &P4DIR, &DMEM_234
        mov.b #0xa5,  &P4DIR
        mov.b &P4DIR, &DMEM_235

        mov.b #0xcd,  &P4SEL         ; P4SEL
        mov.b &P4SEL, &DMEM_236
        mov.b #0x32,  &P4SEL
        mov.b &P4SEL, &DMEM_237

        mov.b #0x00,  &P4IN          ; Re-Initialize
        mov.b #0x00,  &P4OUT
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL

        mov   #0x0004, r15


        /* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P5IN          ; P5IN
        mov.b &P5IN,  &DMEM_240
        mov.b #0x55,  &P5IN
        mov.b &P5IN,  &DMEM_241

        mov.b #0xaa,  &P5OUT         ; P5OUT
        mov.b &P5OUT, &DMEM_242
        mov.b #0x55,  &P5OUT
        mov.b &P5OUT, &DMEM_243

        mov.b #0x5a,  &P5DIR         ; P5DIR
        mov.b &P5DIR, &DMEM_244
        mov.b #0xa5,  &P5DIR
        mov.b &P5DIR, &DMEM_245

        mov.b #0xcd,  &P5SEL         ; P5SEL
        mov.b &P5SEL, &DMEM_246
        mov.b #0x32,  &P5SEL
        mov.b &P5SEL, &DMEM_247

        mov.b #0x00,  &P5IN          ; Re-Initialize
        mov.b #0x00,  &P5OUT
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL

        mov   #0x0005, r15


        /* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P6IN          ; P6IN
        mov.b &P6IN,  &DMEM_250
        mov.b #0x55,  &P6IN
        mov.b &P6IN,  &DMEM_251

        mov.b #0xaa,  &P6OUT         ; P6OUT
        mov.b &P6OUT, &DMEM_252
        mov.b #0x55,  &P6OUT
        mov.b &P6OUT, &DMEM_253

        mov.b #0x5a,  &P6DIR         ; P6DIR
        mov.b &P6DIR, &DMEM_254
        mov.b #0xa5,  &P6DIR
        mov.b &P6DIR, &DMEM_255

        mov.b #0xcd,  &P6SEL         ; P6SEL
        mov.b &P6SEL, &DMEM_256
        mov.b #0x32,  &P6SEL
        mov.b &P6SEL, &DMEM_257

        mov.b #0x00,  &P6IN          ; Re-Initialize
        mov.b #0x00,  &P6OUT
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL

        mov   #0x0006, r15


        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_200, r15        ;# Test Input path
        nop
p1_din_loop:
        mov.b &P1IN,  0(r15)
        inc      r15
        cmp     #DMEM_208, r15
        jne     p1_din_loop


        mov.b #0x01,   &P1OUT       ; Test Output path
        mov   #0x1100, r15
p1_dout_loop:
        rla.b &P1OUT
        inc      r15
        cmp     #0x1107, r15
        jne     p1_dout_loop


        mov.b #0x01,   &P1DIR       ; Test Direction register
        mov   #0x1200, r15
p1_dir_loop:
        rla.b &P1DIR
        inc      r15
        cmp     #0x1207, r15
        jne     p1_dir_loop

        
        mov.b #0x01,   &P1SEL       ; Test Function Select register
        mov   #0x1300, r15
p1_sel_loop:
        rla.b &P1SEL
        inc      r15
        cmp     #0x1307, r15
        jne     p1_sel_loop

        
        mov.b #0x00,  &P1OUT        ; Re-Initialize
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1SEL


        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_210, r15        ;# Test Input path
        nop
p2_din_loop:
        mov.b &P2IN,  0(r15)
        inc      r15
        cmp     #DMEM_218, r15
        jne     p2_din_loop


        mov.b #0x01,   &P2OUT       ; Test Output path
        mov   #0x2100, r15
p2_dout_loop:
        rla.b &P2OUT
        inc      r15
        cmp     #0x2107, r15
        jne     p2_dout_loop


        mov.b #0x01,   &P2DIR       ; Test Direction register
        mov   #0x2200, r15
p2_dir_loop:
        rla.b &P2DIR
        inc      r15
        cmp     #0x2207, r15
        jne     p2_dir_loop

        
        mov.b #0x01,   &P2SEL       ; Test Function Select register
        mov   #0x2300, r15
p2_sel_loop:
        rla.b &P2SEL
        inc      r15
        cmp     #0x2307, r15
        jne     p2_sel_loop

        
        mov.b #0x00,  &P2OUT        ; Re-Initialize
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2SEL


        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_220, r15        ;# Test Input path
        nop
p3_din_loop:
        mov.b &P3IN,  0(r15)
        inc      r15
        cmp     #DMEM_228, r15
        jne     p3_din_loop


        mov.b #0x01,   &P3OUT       ; Test Output path
        mov   #0x3100, r15
p3_dout_loop:
        rla.b &P3OUT
        inc      r15
        cmp     #0x3107, r15
        jne     p3_dout_loop


        mov.b #0x01,   &P3DIR       ; Test Direction register
        mov   #0x3200, r15
p3_dir_loop:
        rla.b &P3DIR
        inc      r15
        cmp     #0x3207, r15
        jne     p3_dir_loop


        mov.b #0x01,   &P3SEL       ; Test Function Select register
        mov   #0x3300, r15
p3_sel_loop:
        rla.b &P3SEL
        inc      r15
        cmp     #0x3307, r15
        jne     p3_sel_loop

        
        mov.b #0x00,  &P3OUT        ; Re-Initialize
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL


        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_230, r15        ;# Test Input path
        nop
p4_din_loop:
        mov.b &P4IN,  0(r15)
        inc      r15
        cmp     #DMEM_238, r15
        jne     p4_din_loop


        mov.b #0x01,   &P4OUT       ; Test Output path
        mov   #0x4100, r15
p4_dout_loop:
        rla.b &P4OUT
        inc      r15
        cmp     #0x4107, r15
        jne     p4_dout_loop


        mov.b #0x01,   &P4DIR       ; Test Direction register
        mov   #0x4200, r15
p4_dir_loop:
        rla.b &P4DIR
        inc      r15
        cmp     #0x4207, r15
        jne     p4_dir_loop


        mov.b #0x01,   &P4SEL       ; Test Function Select register
        mov   #0x4300, r15
p4_sel_loop:
        rla.b &P4SEL
        inc      r15
        cmp     #0x4307, r15
        jne     p4_sel_loop

        
        mov.b #0x00,  &P4OUT        ; Re-Initialize
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL


        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_240, r15        ;# Test Input path
        nop
p5_din_loop:
        mov.b &P5IN,  0(r15)
        inc      r15
        cmp     #DMEM_248, r15
        jne     p5_din_loop


        mov.b #0x01,   &P5OUT       ; Test Output path
        mov   #0x5100, r15
p5_dout_loop:
        rla.b &P5OUT
        inc      r15
        cmp     #0x5107, r15
        jne     p5_dout_loop


        mov.b #0x01,   &P5DIR       ; Test Direction register
        mov   #0x5200, r15
p5_dir_loop:
        rla.b &P5DIR
        inc      r15
        cmp     #0x5207, r15
        jne     p5_dir_loop


        mov.b #0x01,   &P5SEL       ; Test Function Select register
        mov   #0x5300, r15
p5_sel_loop:
        rla.b &P5SEL
        inc      r15
        cmp     #0x5307, r15
        jne     p5_sel_loop

        
        mov.b #0x00,  &P5OUT        ; Re-Initialize
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL


        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */

        mov     #DMEM_250, r15        ;# Test Input path
        nop
p6_din_loop:
        mov.b &P6IN,  0(r15)
        inc      r15
        cmp     #DMEM_258, r15
        jne     p6_din_loop


        mov.b #0x01,   &P6OUT       ; Test Output path
        mov   #0x6100, r15
p6_dout_loop:
        rla.b &P6OUT
        inc      r15
        cmp     #0x6107, r15
        jne     p6_dout_loop


        mov.b #0x01,   &P6DIR       ; Test Direction register
        mov   #0x6200, r15
p6_dir_loop:
        rla.b &P6DIR
        inc      r15
        cmp     #0x6207, r15
        jne     p6_dir_loop


        mov.b #0x01,   &P6SEL       ; Test Function Select register
        mov   #0x6300, r15
p6_sel_loop:
        rla.b &P6SEL
        inc      r15
        cmp     #0x6307, r15
        jne     p6_sel_loop

        
        mov.b #0x00,  &P6OUT        ; Re-Initialize
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL



        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.