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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Rev 18

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DIGITAL I/O                                    */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface:                                           */
/*                                   - Read/Write register access.           */
/*                                   - I/O Functionality.                    */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/

.global main

.set   P1IN,  0x0020
.set   P1OUT, 0x0021
.set   P1DIR, 0x0022
.set   P1IFG, 0x0023
.set   P1IES, 0x0024
.set   P1IE,  0x0025
.set   P1SEL, 0x0026
.set   P2IN,  0x0028
.set   P2OUT, 0x0029
.set   P2DIR, 0x002A
.set   P2IFG, 0x002B
.set   P2IES, 0x002C
.set   P2IE,  0x002D
.set   P2SEL, 0x002E
.set   P3IN,  0x0018
.set   P3OUT, 0x0019
.set   P3DIR, 0x001A
.set   P3SEL, 0x001B
.set   P4IN,  0x001C
.set   P4OUT, 0x001D
.set   P4DIR, 0x001E
.set   P4SEL, 0x001F
.set   P5IN,  0x0030
.set   P5OUT, 0x0031
.set   P5DIR, 0x0032
.set   P5SEL, 0x0033
.set   P6IN,  0x0034
.set   P6OUT, 0x0035
.set   P6DIR, 0x0036
.set   P6SEL, 0x0037

main:
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P1IN          ; P1IN
        mov.b &P1IN,  &0x0200
        mov.b #0x55,  &P1IN
        mov.b &P1IN,  &0x0201

        mov.b #0xaa,  &P1OUT         ; P1OUT
        mov.b &P1OUT, &0x0202
        mov.b #0x55,  &P1OUT
        mov.b &P1OUT, &0x0203

        mov.b #0x5a,  &P1DIR         ; P1DIR
        mov.b &P1DIR, &0x0204
        mov.b #0xa5,  &P1DIR
        mov.b &P1DIR, &0x0205

        mov.b #0x55,  &P1IFG         ; P1IFG
        mov.b &P1IFG, &0x0206
        mov.b #0xaa,  &P1IFG
        mov.b &P1IFG, &0x0207

        mov.b #0xa5,  &P1IES         ; P1IES
        mov.b &P1IES, &0x0208
        mov.b #0x5a,  &P1IES
        mov.b &P1IES, &0x0209

        mov.b #0xaa,  &P1IE          ; P1IE
        mov.b &P1IE,  &0x020A
        mov.b #0x55,  &P1IE
        mov.b &P1IE,  &0x020B

        mov.b #0xcd,  &P1SEL         ; P1SEL
        mov.b &P1SEL, &0x020C
        mov.b #0x32,  &P1SEL
        mov.b &P1SEL, &0x020D


        mov.b #0x00,  &P1IN          ; Re-Initialize
        mov.b #0x00,  &P1OUT
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1IFG
        mov.b #0x00,  &P1IES
        mov.b #0x00,  &P1IE
        mov.b #0x00,  &P1SEL

        mov   #0x0001, r15


        /* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P2IN          ; P2IN
        mov.b &P2IN,  &0x0210
        mov.b #0x55,  &P2IN
        mov.b &P2IN,  &0x0211

        mov.b #0xaa,  &P2OUT         ; P2OUT
        mov.b &P2OUT, &0x0212
        mov.b #0x55,  &P2OUT
        mov.b &P2OUT, &0x0213

        mov.b #0x5a,  &P2DIR         ; P2DIR
        mov.b &P2DIR, &0x0214
        mov.b #0xa5,  &P2DIR
        mov.b &P2DIR, &0x0215

        mov.b #0x55,  &P2IFG         ; P2IFG
        mov.b &P2IFG, &0x0216
        mov.b #0xaa,  &P2IFG
        mov.b &P2IFG, &0x0217

        mov.b #0xa5,  &P2IES         ; P2IES
        mov.b &P2IES, &0x0218
        mov.b #0x5a,  &P2IES
        mov.b &P2IES, &0x0219

        mov.b #0xaa,  &P2IE          ; P2IE
        mov.b &P2IE,  &0x021A
        mov.b #0x55,  &P2IE
        mov.b &P2IE,  &0x021B

        mov.b #0xcd,  &P2SEL         ; P2SEL
        mov.b &P2SEL, &0x021C
        mov.b #0x32,  &P2SEL
        mov.b &P2SEL, &0x021D

        mov.b #0x00,  &P2IN          ; Re-Initialize
        mov.b #0x00,  &P2OUT
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2IFG
        mov.b #0x00,  &P2IES
        mov.b #0x00,  &P2IE
        mov.b #0x00,  &P2SEL

        mov   #0x0002, r15


        /* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P3IN          ; P3IN
        mov.b &P3IN,  &0x0220
        mov.b #0x55,  &P3IN
        mov.b &P3IN,  &0x0221

        mov.b #0xaa,  &P3OUT         ; P3OUT
        mov.b &P3OUT, &0x0222
        mov.b #0x55,  &P3OUT
        mov.b &P3OUT, &0x0223

        mov.b #0x5a,  &P3DIR         ; P3DIR
        mov.b &P3DIR, &0x0224
        mov.b #0xa5,  &P3DIR
        mov.b &P3DIR, &0x0225

        mov.b #0xcd,  &P3SEL         ; P3SEL
        mov.b &P3SEL, &0x0226
        mov.b #0x32,  &P3SEL
        mov.b &P3SEL, &0x0227

        mov.b #0x00,  &P3IN          ; Re-Initialize
        mov.b #0x00,  &P3OUT
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL

        mov   #0x0003, r15


        /* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P4IN          ; P4IN
        mov.b &P4IN,  &0x0230
        mov.b #0x55,  &P4IN
        mov.b &P4IN,  &0x0231

        mov.b #0xaa,  &P4OUT         ; P4OUT
        mov.b &P4OUT, &0x0232
        mov.b #0x55,  &P4OUT
        mov.b &P4OUT, &0x0233

        mov.b #0x5a,  &P4DIR         ; P4DIR
        mov.b &P4DIR, &0x0234
        mov.b #0xa5,  &P4DIR
        mov.b &P4DIR, &0x0235

        mov.b #0xcd,  &P4SEL         ; P4SEL
        mov.b &P4SEL, &0x0236
        mov.b #0x32,  &P4SEL
        mov.b &P4SEL, &0x0237

        mov.b #0x00,  &P4IN          ; Re-Initialize
        mov.b #0x00,  &P4OUT
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL

        mov   #0x0004, r15


        /* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P5IN          ; P5IN
        mov.b &P5IN,  &0x0240
        mov.b #0x55,  &P5IN
        mov.b &P5IN,  &0x0241

        mov.b #0xaa,  &P5OUT         ; P5OUT
        mov.b &P5OUT, &0x0242
        mov.b #0x55,  &P5OUT
        mov.b &P5OUT, &0x0243

        mov.b #0x5a,  &P5DIR         ; P5DIR
        mov.b &P5DIR, &0x0244
        mov.b #0xa5,  &P5DIR
        mov.b &P5DIR, &0x0245

        mov.b #0xcd,  &P5SEL         ; P5SEL
        mov.b &P5SEL, &0x0246
        mov.b #0x32,  &P5SEL
        mov.b &P5SEL, &0x0247

        mov.b #0x00,  &P5IN          ; Re-Initialize
        mov.b #0x00,  &P5OUT
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL

        mov   #0x0005, r15


        /* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */

        mov.b #0xaa,  &P6IN          ; P6IN
        mov.b &P6IN,  &0x0250
        mov.b #0x55,  &P6IN
        mov.b &P6IN,  &0x0251

        mov.b #0xaa,  &P6OUT         ; P6OUT
        mov.b &P6OUT, &0x0252
        mov.b #0x55,  &P6OUT
        mov.b &P6OUT, &0x0253

        mov.b #0x5a,  &P6DIR         ; P6DIR
        mov.b &P6DIR, &0x0254
        mov.b #0xa5,  &P6DIR
        mov.b &P6DIR, &0x0255

        mov.b #0xcd,  &P6SEL         ; P6SEL
        mov.b &P6SEL, &0x0256
        mov.b #0x32,  &P6SEL
        mov.b &P6SEL, &0x0257

        mov.b #0x00,  &P6IN          ; Re-Initialize
        mov.b #0x00,  &P6OUT
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL

        mov   #0x0006, r15


        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0200, r15        ;# Test Input path
p1_din_loop:
        mov.b &P1IN,  0(r15)
        inc      r15
        cmp     #0x0208, r15
        jne     p1_din_loop


        mov.b #0x01,   &P1OUT       ; Test Output path
        mov   #0x1100, r15
p1_dout_loop:
        rla.b &P1OUT
        inc      r15
        cmp     #0x1107, r15
        jne     p1_dout_loop


        mov.b #0x01,   &P1DIR       ; Test Direction register
        mov   #0x1200, r15
p1_dir_loop:
        rla.b &P1DIR
        inc      r15
        cmp     #0x1207, r15
        jne     p1_dir_loop

        
        mov.b #0x01,   &P1SEL       ; Test Function Select register
        mov   #0x1300, r15
p1_sel_loop:
        rla.b &P1SEL
        inc      r15
        cmp     #0x1307, r15
        jne     p1_sel_loop

        
        mov.b #0x00,  &P1OUT        ; Re-Initialize
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1SEL


        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0210, r15        ;# Test Input path
p2_din_loop:
        mov.b &P2IN,  0(r15)
        inc      r15
        cmp     #0x0218, r15
        jne     p2_din_loop


        mov.b #0x01,   &P2OUT       ; Test Output path
        mov   #0x2100, r15
p2_dout_loop:
        rla.b &P2OUT
        inc      r15
        cmp     #0x2107, r15
        jne     p2_dout_loop


        mov.b #0x01,   &P2DIR       ; Test Direction register
        mov   #0x2200, r15
p2_dir_loop:
        rla.b &P2DIR
        inc      r15
        cmp     #0x2207, r15
        jne     p2_dir_loop

        
        mov.b #0x01,   &P2SEL       ; Test Function Select register
        mov   #0x2300, r15
p2_sel_loop:
        rla.b &P2SEL
        inc      r15
        cmp     #0x2307, r15
        jne     p2_sel_loop

        
        mov.b #0x00,  &P2OUT        ; Re-Initialize
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2SEL


        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0220, r15        ;# Test Input path
p3_din_loop:
        mov.b &P3IN,  0(r15)
        inc      r15
        cmp     #0x0228, r15
        jne     p3_din_loop


        mov.b #0x01,   &P3OUT       ; Test Output path
        mov   #0x3100, r15
p3_dout_loop:
        rla.b &P3OUT
        inc      r15
        cmp     #0x3107, r15
        jne     p3_dout_loop


        mov.b #0x01,   &P3DIR       ; Test Direction register
        mov   #0x3200, r15
p3_dir_loop:
        rla.b &P3DIR
        inc      r15
        cmp     #0x3207, r15
        jne     p3_dir_loop


        mov.b #0x01,   &P3SEL       ; Test Function Select register
        mov   #0x3300, r15
p3_sel_loop:
        rla.b &P3SEL
        inc      r15
        cmp     #0x3307, r15
        jne     p3_sel_loop

        
        mov.b #0x00,  &P3OUT        ; Re-Initialize
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL


        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0230, r15        ;# Test Input path
p4_din_loop:
        mov.b &P4IN,  0(r15)
        inc      r15
        cmp     #0x0238, r15
        jne     p4_din_loop


        mov.b #0x01,   &P4OUT       ; Test Output path
        mov   #0x4100, r15
p4_dout_loop:
        rla.b &P4OUT
        inc      r15
        cmp     #0x4107, r15
        jne     p4_dout_loop


        mov.b #0x01,   &P4DIR       ; Test Direction register
        mov   #0x4200, r15
p4_dir_loop:
        rla.b &P4DIR
        inc      r15
        cmp     #0x4207, r15
        jne     p4_dir_loop


        mov.b #0x01,   &P4SEL       ; Test Function Select register
        mov   #0x4300, r15
p4_sel_loop:
        rla.b &P4SEL
        inc      r15
        cmp     #0x4307, r15
        jne     p4_sel_loop

        
        mov.b #0x00,  &P4OUT        ; Re-Initialize
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL


        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0240, r15        ;# Test Input path
p5_din_loop:
        mov.b &P5IN,  0(r15)
        inc      r15
        cmp     #0x0248, r15
        jne     p5_din_loop


        mov.b #0x01,   &P5OUT       ; Test Output path
        mov   #0x5100, r15
p5_dout_loop:
        rla.b &P5OUT
        inc      r15
        cmp     #0x5107, r15
        jne     p5_dout_loop


        mov.b #0x01,   &P5DIR       ; Test Direction register
        mov   #0x5200, r15
p5_dir_loop:
        rla.b &P5DIR
        inc      r15
        cmp     #0x5207, r15
        jne     p5_dir_loop


        mov.b #0x01,   &P5SEL       ; Test Function Select register
        mov   #0x5300, r15
p5_sel_loop:
        rla.b &P5SEL
        inc      r15
        cmp     #0x5307, r15
        jne     p5_sel_loop

        
        mov.b #0x00,  &P5OUT        ; Re-Initialize
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL


        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */

        mov     #0x0250, r15        ;# Test Input path
p6_din_loop:
        mov.b &P6IN,  0(r15)
        inc      r15
        cmp     #0x0258, r15
        jne     p6_din_loop


        mov.b #0x01,   &P6OUT       ; Test Output path
        mov   #0x6100, r15
p6_dout_loop:
        rla.b &P6OUT
        inc      r15
        cmp     #0x6107, r15
        jne     p6_dout_loop


        mov.b #0x01,   &P6DIR       ; Test Direction register
        mov   #0x6200, r15
p6_dir_loop:
        rla.b &P6DIR
        inc      r15
        cmp     #0x6207, r15
        jne     p6_dir_loop


        mov.b #0x01,   &P6SEL       ; Test Function Select register
        mov   #0x6300, r15
p6_sel_loop:
        rla.b &P6SEL
        inc      r15
        cmp     #0x6307, r15
        jne     p6_sel_loop

        
        mov.b #0x00,  &P6OUT        ; Re-Initialize
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL



        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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