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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_mpy.s43] - Rev 86
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* HARDWARE MULTIPLIER */
/*---------------------------------------------------------------------------*/
/* Test the hardware multiplier: */
/* - MPY mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 18 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
.global main
.set WDTCTL, 0x0120
.set MPY, 0x0130
.set MPYS, 0x0132
.set MAC, 0x0134
.set MACS, 0x0136
.set OP2, 0x0138
.set RESLO, 0x013A
.set RESHI, 0x013C
.set SUMEXT, 0x013E
main:
/* -------------- UNSIGNED MULTIPLICATION --------------- */
;; Disable watchdog
mov #0x5A80, &WDTCTL
;; Initialize variables
mov #0x0000, R15
mov #0x0000, R8
mov #0x0000, R9
mpy_loop:
;; Initialize RESLO and RESHI to make sure it is overwritten
mov #0x0000, &RESLO
mov #0xC000, &RESHI
;; Perform unsigned R8*R9
mov R8, &MPY
mov R9, &OP2
;; Read result
mov &RESLO, R10
mov &RESHI, R11
mov &SUMEXT, R12
;; Notify verilog checker
add #1, R15
;; Update next OP1 (R8)
cmp #0xF0F0, R8
jeq op2_update
mov #0x00FF, R7
and R8, R7
cmp #0x00F0, R7
jeq op1_hi_update
add #0x0010, R8
jmp mpy_loop
op1_hi_update:
and #0xff00, R8
add #0x1000, R8
jmp mpy_loop
;; Update next OP2 (R9)
op2_update:
cmp #0xF0F0, R9
jeq end_of_test
mov #0x0000, R8
mov #0x00FF, R7
and R9, R7
cmp #0x00F0, R7
jeq op2_hi_update
add #0x0010, R9
jmp mpy_loop
op2_hi_update:
and #0xff00, R9
add #0x1000, R9
jmp mpy_loop
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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