OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sfr.s43] - Rev 172

Go to most recent revision | Compare with Previous | Blame | View Log

/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                  Special Function Registers (SFRs)                        */
/*---------------------------------------------------------------------------*/
/* Test the SFR registers.                                                   */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/

.include "pmem_defs.asm"

.global main

main:

        /* -------   NMI             ------ */

        mov   #0x1000, r15

        ;; NMI feature is verified in the NMI.S43 test

        mov   #0x1001, r15
        

        /* -------   WATCHDOG        ------ */

        mov   #0x2000, r15

        ;; WATCHDOG feature is verified in the WDT_*.S43 tests
        mov   #0x5a90, &WDTCTL    ;# Enable interval mode & disable timer
                
        mov   #0x2001, r15

        
        /* -------   READ/WRITE IFG1       ------ */

        mov   #0x3000, r15

        mov   &IFG1,   r10
        mov   #0x3001, r15

        mov   #0x5555, &IFG1
        mov   &IFG1,   r10
        mov   #0x3002, r15
        
        mov   #0xAAAA, &IFG1
        mov   &IFG1,   r10
        mov   #0x3003, r15

        mov.b #0x55,   &IFG1
        mov.b &IFG1,   r10
        mov   #0x3004, r15
        
        mov.b #0xAA,    &IFG1_HI
        mov.b &IFG1_HI, r10
        mov   #0x3005,  r15

        mov   #0x0000, &IFG1
        mov   &IFG1,   r10
        mov   #0x3006, r15
        
        
        /* -------   READ/WRITE IE1         ------ */
        
        mov   #0x4000, r15

        mov   &IE1,    r10
        mov   #0x4001, r15

        mov   #0x5555, &IE1
        mov   &IE1,    r10
        mov   #0x4002, r15
        
        mov   #0xAAAA, &IE1
        mov   &IE1,    r10
        mov   #0x4003, r15
        
        mov.b #0x55,   &IE1
        mov.b &IE1,    r10
        mov   #0x4004, r15
        
        mov.b #0xAA,    &IE1_HI
        mov.b &IE1_HI,  r10
        mov   #0x4005,  r15

        mov   #0x0000, &IE1
        mov   &IE1,    r10
        mov   #0x4006, r15
        
        
        /* -------   READ/WRITE CPU_ID     ------ */

        mov   #0x5000, r15

        mov   &CPU_ID_LO, r10
        mov   &CPU_ID_HI, r11
        mov   #0x5001, r15

        mov   0x5554,     &CPU_ID_LO
        mov   0xAAAA,     &CPU_ID_HI
        mov   &CPU_ID_LO, r10
        mov   &CPU_ID_HI, r11
        mov   #0x5002, r15
                
        mov   0xAAAA,     &CPU_ID_LO
        mov   0x5554,     &CPU_ID_HI
        mov   &CPU_ID_LO, r10
        mov   &CPU_ID_HI, r11           
        mov   #0x5003, r15


        /* -------   READ/WRITE CPU_NR     ------ */

        mov   #0x6000, r15

        mov   &CPU_NR, r10
        mov   #0x6001, r15

        mov   0x5554,  &CPU_NR
        mov   &CPU_NR, r10
        mov   #0x6002, r15
                
        mov   0xAAAA,  &CPU_NR
        mov   &CPU_NR, r10
        mov   #0x6003, r15


                
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff



        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test     ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test     ; Interrupt  1                      <unused>
.word end_of_test     ; Interrupt  2                      <unused>
.word end_of_test     ; Interrupt  3                      <unused>
.word end_of_test     ; Interrupt  4                      <unused>
.word end_of_test     ; Interrupt  5                      <unused>
.word end_of_test     ; Interrupt  6                      <unused>
.word end_of_test     ; Interrupt  7                      <unused>
.word end_of_test     ; Interrupt  8                      <unused>
.word end_of_test     ; Interrupt  9                      <unused>
.word end_of_test     ; Interrupt 10                      Watchdog timer
.word end_of_test     ; Interrupt 11                      <unused>
.word end_of_test     ; Interrupt 12                      <unused>
.word end_of_test     ; Interrupt 13                      <unused>
.word end_of_test     ; Interrupt 14                      NMI
.word main            ; Interrupt 15 (highest priority)   RESET

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.