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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_push_rom-rd.s43] - Rev 85
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* PUSH: DATA READ ACCESS FROM ROM */
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction with all addressing modes making a read access */
/* to the ROM. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
.global main
main:
/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
# Initialization
#------------------------
mov #0x0020, r4 ;# Initialize RAM
mov #0x0230, r5
clear_mem_loop:
clr 0(r5)
incd r5
dec r4
jnz clear_mem_loop
mov #0x0252, r1 ;# Initialize stack pointer
mov #0x1000, r15
# Addressing mode: @Rn
#------------------------
mov #data_aRn_0x1234, r4
push @r4 ;# PUSH (0x1234 => @=0x0250)
mov #data_aRn_0x5678, r6
push @r6 ;# PUSH (0x5678 => @=0x024E)
mov #0x2000, r15
# Addressing mode: @Rn+
#------------------------
mov #data_aRni_0x9abc, r4
push @r4+ ;# PUSH (0x9abc => @=0x024C)
push @r4+ ;# PUSH (0xdef0 => @=0x024A)
mov #0x3000, r15
# Addressing mode: X(Rn)
#------------------------
mov #data_xRn_0x0fed, r4
push 26(r4) ;# PUSH (0x0fed => @=0x0248)
push 28(r4) ;# PUSH (0xcba9 => @=0x0246)
mov #0x4000, r15
# Addressing mode: EDE
#------------------------
.set EDE_21E, (__data_start+0x001E)
.set EDE_220, (__data_start+0x0020)
push data_EDE_0x8765 ;# PUSH (0x8765 => @=0x0244)
push data_EDE_0x4321 ;# PUSH (0x4321 => @=0x0242)
mov #0x5000, r15
# Addressing mode: &EDE
#------------------------
.set aEDE_222, 0x0222
.set aEDE_224, 0x0224
push &data_aEDE_0x1f2e ;# PUSH (0x1f2e => @=0x0240)
push &data_aEDE_0x3d4c ;# PUSH (0x3d4c => @=0x023E)
mov #0x6000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- DATA TABLE --------------- */
data_aRn_0x1234:
.word 0x1234
data_aRn_0x5678:
.word 0x5678
data_aRni_0x9abc:
.word 0x9abc
.word 0xdef0
data_xRn_0x0fed:
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0000
.word 0x0fed
.word 0xcba9
data_EDE_0x8765:
.word 0x8765
data_EDE_0x4321:
.word 0x4321
data_aEDE_0x1f2e:
.word 0x1f2e
data_aEDE_0x3d4c:
.word 0x3d4c
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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