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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: CALL  INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the CALL  instruction.                                               */
/*===========================================================================*/


.global main

        mov     #0x1234, r3
        mov     #0x1234, r4
        mov     #0x1234, r5
        mov     #0x1234, r6
        mov     #0x1234, r7
        mov     #0x1234, r8
        mov     #0x1234, r9
        mov     #0x1234, r10
        mov     #0x1234, r11
        mov     #0x1234, r12
        mov     #0x1234, r13
        mov     #0x1234, r14
main:
        # Test RESET vector
        #------------------------
        mov     #0x1000, r15


        # Test RETI instruction
        #------------------------

        # Pre-initialize stack
        mov             #0x0252, r1
        push #RETI_ROUTINE
        push            #0x0145
        mov     #0x0000, &0x0200

        # Run RETI test
        mov     #0x0000, r2
        mov     #0x0000, r5
        reti
end_of_reti_test:

        mov     #0x2000, r15


        # Test IRQ  0
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x3000, r15

wait_irq00:
        cmp     #0x5678, r6
        jne     wait_irq00

        mov     #0x3001, r15


        # Test IRQ  1
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x4000, r15

wait_irq01:
        cmp     #0x9abc, r6
        jne     wait_irq01

        mov     #0x4001, r15


        # Test IRQ  2
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x5000, r15

wait_irq02:
        cmp     #0xdef1, r6
        jne     wait_irq02

        mov     #0x5001, r15


        # Test IRQ  3
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x6000, r15

wait_irq03:
        cmp     #0x2345, r6
        jne     wait_irq03

        mov     #0x6001, r15


        # Test IRQ  4
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x7000, r15

wait_irq04:
        cmp     #0x6789, r6
        jne     wait_irq04

        mov     #0x7001, r15


        # Test IRQ  5
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x8000, r15

wait_irq05:
        cmp     #0xabcd, r6
        jne     wait_irq05

        mov     #0x8001, r15


        # Test IRQ  6
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x9000, r15

wait_irq06:
        cmp     #0xef12, r6
        jne     wait_irq06

        mov     #0x9001, r15


        # Test IRQ  7
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xa000, r15

wait_irq07:
        cmp     #0x3456, r6
        jne     wait_irq07

        mov     #0xa001, r15


        # Test IRQ  8
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xb000, r15

wait_irq08:
        cmp     #0x789a, r6
        jne     wait_irq08

        mov     #0xb001, r15


        # Test IRQ  9
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xc000, r15

wait_irq09:
        cmp     #0xbcde, r6
        jne     wait_irq09

        mov     #0xc001, r15


        # Test IRQ 10
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xd000, r15

wait_irq10:
        cmp     #0xf123, r6
        jne     wait_irq10

        mov     #0xd001, r15


        # Test IRQ 11
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xe000, r15

wait_irq11:
        cmp     #0x4567, r6
        jne     wait_irq11

        mov     #0xe001, r15


        # Test IRQ 12
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf000, r15

wait_irq12:
        cmp     #0x89ab, r6
        jne     wait_irq12

        mov     #0xf001, r15


        # Test IRQ 13
        #-------------------------

        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf100, r15

wait_irq13:
        cmp     #0xcdef, r6
        jne     wait_irq13

        mov     #0xf101, r15


        # Test IRQ NMI:  rising edge
        #----------------------------
.set   WDTCTL, 0x0120
.set   IE1,    0x0000
.set   IFG1,   0x0002

        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
        bic.b   #0x0010, &IFG1    ; Clear NMI flag
        bis.b   #0x0010, &IE1     ; Enable NMI

        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf200, r15

wait_nmi:
        mov     #0xa5a5, &0x0200
        cmp     #0x0123, r6
        jne    wait_nmi

        mov.b      &IE1,  r9
        mov.b      &IFG1, r10

        mov     #0xf201, r15



        /* ----------------------    END OF TEST   --------------- */
end_of_test:
        nop
        br #0xffff



        /* ----------------------    FUNCTIONS    --------------- */

RETI_ROUTINE:
        mov #0x1234, r5
        jmp end_of_reti_test


IRQ00_ROUTINE:
        mov #0x5678, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ01_ROUTINE:
        mov #0x9abc, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ02_ROUTINE:
        mov #0xdef1, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ03_ROUTINE:
        mov #0x2345, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ04_ROUTINE:
        mov #0x6789, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ05_ROUTINE:
        mov #0xabcd, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ06_ROUTINE:
        mov #0xef12, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ07_ROUTINE:
        mov #0x3456, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ08_ROUTINE:
        mov #0x789a, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ09_ROUTINE:
        mov #0xbcde, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ10_ROUTINE:
        mov #0xf123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ11_ROUTINE:
        mov #0x4567, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ12_ROUTINE:
        mov #0x89ab, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

IRQ13_ROUTINE:
        mov #0xcdef, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

NMI_ROUTINE:
        mov #0x0123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti

        nop
        nop
        nop
        nop
        nop



        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word IRQ00_ROUTINE     ; Interrupt  0 (lowest priority)    <unused>
.word IRQ01_ROUTINE     ; Interrupt  1                      <unused>
.word IRQ02_ROUTINE     ; Interrupt  2                      <unused>
.word IRQ03_ROUTINE     ; Interrupt  3                      <unused>
.word IRQ04_ROUTINE     ; Interrupt  4                      <unused>
.word IRQ05_ROUTINE     ; Interrupt  5                      <unused>
.word IRQ06_ROUTINE     ; Interrupt  6                      <unused>
.word IRQ07_ROUTINE     ; Interrupt  7                      <unused>
.word IRQ08_ROUTINE     ; Interrupt  8                      <unused>
.word IRQ09_ROUTINE     ; Interrupt  9                      <unused>
.word IRQ10_ROUTINE     ; Interrupt 10                      Watchdog timer
.word IRQ11_ROUTINE     ; Interrupt 11                      <unused>
.word IRQ12_ROUTINE     ; Interrupt 12                      <unused>
.word IRQ13_ROUTINE     ; Interrupt 13                      <unused>
.word NMI_ROUTINE       ; Interrupt 14                      NMI
.word main              ; Interrupt 15 (highest priority)   RESET

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