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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: RRA[.B] INSTRUCTION            */
/*---------------------------------------------------------------------------*/
/* Test the RRA[.B] instruction.                                             */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/

.set    DMEM_BASE, (__data_start     )
.set    DMEM_200,  (__data_start+0x00)
.set    DMEM_202,  (__data_start+0x02)
.set    DMEM_204,  (__data_start+0x04)
.set    DMEM_206,  (__data_start+0x06)
.set    DMEM_208,  (__data_start+0x08)
.set    DMEM_209,  (__data_start+0x09)
.set    DMEM_20A,  (__data_start+0x0A)
.set    DMEM_20B,  (__data_start+0x0B)
.set    DMEM_20C,  (__data_start+0x0C)
.set    DMEM_20D,  (__data_start+0x0D)
.set    DMEM_20E,  (__data_start+0x0E)
.set    DMEM_20F,  (__data_start+0x0F)
.set    DMEM_210,  (__data_start+0x10)
.set    DMEM_212,  (__data_start+0x12)
.set    DMEM_214,  (__data_start+0x14)
.set    DMEM_216,  (__data_start+0x16)
.set    DMEM_218,  (__data_start+0x18)
.set    DMEM_219,  (__data_start+0x19)
.set    DMEM_21A,  (__data_start+0x1A)
.set    DMEM_21B,  (__data_start+0x1B)
.set    DMEM_21C,  (__data_start+0x1C)
.set    DMEM_21D,  (__data_start+0x1D)
.set    DMEM_21E,  (__data_start+0x1E)
.set    DMEM_21F,  (__data_start+0x1F)
.set    DMEM_220,  (__data_start+0x20)
.set    DMEM_222,  (__data_start+0x22)
.set    DMEM_224,  (__data_start+0x24)
.set    DMEM_226,  (__data_start+0x26)
.set    DMEM_228,  (__data_start+0x28)
.set    DMEM_22A,  (__data_start+0x2A)
.set    DMEM_22C,  (__data_start+0x2C)
.set    DMEM_22E,  (__data_start+0x2E)
.set    DMEM_230,  (__data_start+0x30)
.set    DMEM_232,  (__data_start+0x32)
.set    DMEM_234,  (__data_start+0x34)
.set    DMEM_236,  (__data_start+0x36)
.set    DMEM_238,  (__data_start+0x38)
.set    DMEM_239,  (__data_start+0x39)
.set    DMEM_23A,  (__data_start+0x3A)
.set    DMEM_23B,  (__data_start+0x3B)
.set    DMEM_23C,  (__data_start+0x3C)
.set    DMEM_23D,  (__data_start+0x3D)
.set    DMEM_23E,  (__data_start+0x3E)
.set    DMEM_23F,  (__data_start+0x3F)
.set    DMEM_240,  (__data_start+0x40)
.set    DMEM_242,  (__data_start+0x42)
.set    DMEM_244,  (__data_start+0x44)
.set    DMEM_246,  (__data_start+0x46)
.set    DMEM_248,  (__data_start+0x48)
.set    DMEM_249,  (__data_start+0x49)
.set    DMEM_24A,  (__data_start+0x4A)
.set    DMEM_24B,  (__data_start+0x4B)
.set    DMEM_24C,  (__data_start+0x4C)
.set    DMEM_24D,  (__data_start+0x4D)
.set    DMEM_24E,  (__data_start+0x4E)
.set    DMEM_24F,  (__data_start+0x4F)
.set    DMEM_250,  (__data_start+0x50)

.global main

main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */


        # Addressing mode: Rn
        #------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, r4
        rra          r4            ;# RRA ({r4=0x7332}  => {r4=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, r6
        rra          r6            ;# RRA ({r6=0x7333}  => {r6=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, r8
        rra          r8            ;# RRA ({r9=0x8332}  => {r9=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, r10
        rra         r10            ;# RRA ({r10=0x8333} => {r10=0xc199, C=1})
        mov          r2, r11

        mov     #0x1000, r15


        # Addressing mode: @Rn
        #------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, &DMEM_200
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_202
        rra         @r4            ;# RRA ({mem00=0x7332}  => {mem00=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, &DMEM_202
        mov   #DMEM_202, r6
        mov     #0xaaaa, &DMEM_204
        rra         @r6            ;# RRA ({mem01=0x7333}  => {mem01=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, &DMEM_204
        mov   #DMEM_204, r8
        mov     #0xaaaa, &DMEM_206
        rra         @r8            ;# RRA ({mem02=0x8332}  => {mem02=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, &DMEM_206
        mov   #DMEM_206, r10
        mov     #0xaaaa, &DMEM_208
        rra        @r10            ;# RRA ({mem03=0x8333}  => {mem03=0xc199, C=1})
        mov          r2, r11

        mov     #0x2000, r15


        # Addressing mode: @Rn+
        #------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, &DMEM_208
        mov   #DMEM_208, r4
        mov     #0xaaaa, &DMEM_20A
        rra        @r4+            ;# RRA ({mem04=0x7332}  => {mem04=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, &DMEM_20A
        mov   #DMEM_20A, r6
        mov     #0xaaaa, &DMEM_20C
        rra        @r6+            ;# RRA ({mem05=0x7333}  => {mem05=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, &DMEM_20C
        mov   #DMEM_20C, r8
        mov     #0xaaaa, &DMEM_20E
        rra        @r8+            ;# RRA ({mem06=0x8332}  => {mem06=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, &DMEM_20E
        mov   #DMEM_20E, r10
        mov     #0xaaaa, &DMEM_210
        rra       @r10+            ;# RRA ({mem07=0x8333}  => {mem07=0xc199, C=1})
        mov          r2, r11

        mov     #0x3000, r15


        # Addressing mode: X(Rn)
        #------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, &DMEM_210
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_212
        rra       16(r4)            ;# RRA ({mem08=0x7332}  => {mem08=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, &DMEM_212
        mov   #DMEM_200, r6
        mov     #0xaaaa, &DMEM_214
        rra       18(r6)            ;# RRA ({mem09=0x7333}  => {mem09=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, &DMEM_214
        mov   #DMEM_200, r8
        mov     #0xaaaa, &DMEM_216
        rra       20(r8)            ;# RRA ({mem0a=0x8332}  => {mem0a=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, &DMEM_216
        mov   #DMEM_200, r10
        mov     #0xaaaa, &DMEM_218
        rra      22(r10)            ;# RRA ({mem0b=0x8333}  => {mem0b=0xc199, C=1})
        mov          r2, r11

        mov     #0x4000, r15


        # Addressing mode: EDE
        #------------------------
.set   EDE_218,  DMEM_218
.set   EDE_21A,  DMEM_21A
.set   EDE_21C,  DMEM_21C
.set   EDE_21E,  DMEM_21E

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, &DMEM_218
        mov     #0xaaaa, &DMEM_21A
        rra     EDE_218            ;# RRA ({mem0c=0x7332}  => {mem0c=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, &DMEM_21A
        mov     #0xaaaa, &DMEM_21C
        rra     EDE_21A            ;# RRA ({mem0d=0x7333}  => {mem0d=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, &DMEM_21C
        mov     #0xaaaa, &DMEM_21E
        rra     EDE_21C            ;# RRA ({mem0e=0x8332}  => {mem0e=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, &DMEM_21E
        mov     #0xaaaa, &DMEM_220
        rra     EDE_21E            ;# RRA ({mem0f=0x8333}  => {mem0f=0xc199, C=1})
        mov          r2, r11

        mov     #0x5000, r15


        # Addressing mode: &EDE
        #------------------------
.set   aEDE_220,  DMEM_220
.set   aEDE_222,  DMEM_222
.set   aEDE_224,  DMEM_224
.set   aEDE_226,  DMEM_226

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7332, &DMEM_220
        mov     #0xaaaa, &DMEM_222
        rra   &aEDE_220            ;# RRA ({mem10=0x7332}  => {mem10=0x3999, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7333, &DMEM_222
        mov     #0xaaaa, &DMEM_224
        rra   &aEDE_222            ;# RRA ({mem11=0x7333}  => {mem11=0x3999, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8332, &DMEM_224
        mov     #0xaaaa, &DMEM_226
        rra   &aEDE_224            ;# RRA ({mem12=0x8332}  => {mem12=0xc199, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8333, &DMEM_226
        mov     #0xaaaa, &DMEM_228
        rra   &aEDE_226            ;# RRA ({mem13=0x8333}  => {mem13=0xc199, C=1})
        mov          r2, r11

        mov     #0x6000, r15


        /* ----------------------- CLEAR MEMORY --------------------------- */
        mov     #0x0015, r4
        mov   #DMEM_200, r5
clear_mem_loop:
        clr    0(r5)
        incd     r5
        dec      r4
        jnz     clear_mem_loop 

        mov     #0x7000, r15


        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */

        # Addressing mode: Rn
        #------------------------

        mov     #0x0001, r2    ;# Test 1
        mov     #0xff72, r4
        rra.b        r4        ;# RRA.B ({r4=0x32}  => {r4=0x39, C=0})
        mov          r2, r5

        mov     #0x0001, r2    ;# Test 2
        mov     #0xff73, r6
        rra.b        r6        ;# RRA.B ({r6=0x33}  => {r6=0x39, C=1})
        mov          r2, r7

        mov     #0x0000, r2    ;# Test 3
        mov     #0xf082, r8
        rra.b        r8        ;# RRA.B ({r9=0x32}  => {r9=0xc1, C=0})
        mov          r2, r9

        mov     #0x0000, r2    ;# Test 4
        mov     #0xf083, r10
        rra.b       r10        ;# RRA.B ({r10=0x33} => {r10=0xc1, C=1})
        mov          r2, r11

        mov     #0x8000, r15


        # Addressing mode: @Rn (Low Byte)
        #---------------------------------

        mov     #0x0001, r2        ;# Test 1: Low Byte
        mov     #0x2572, &DMEM_200
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_202
        rra.b       @r4            ;# RRA.B ({mem00=0x2572}  => {mem00=0x2539, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2: Low Byte
        mov     #0x2573, &DMEM_202
        mov   #DMEM_202, r6
        mov     #0xaaaa, &DMEM_204
        rra.b       @r6            ;# RRA.B ({mem01=0x2573}  => {mem01=0x2539, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3: Low Byte
        mov     #0x2582, &DMEM_204
        mov   #DMEM_204, r8
        mov     #0xaaaa, &DMEM_206
        rra.b       @r8            ;# RRA.B ({mem02=0x2582}  => {mem02=0x25c1, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4: Low Byte
        mov     #0x2583, &DMEM_206
        mov   #DMEM_206, r10
        mov     #0xaaaa, &DMEM_208
        rra.b      @r10            ;# RRA.B ({mem03=0x2583}  => {mem03=0x25c1, C=1})
        mov          r2, r11

        mov     #0x9000, r15

        # Addressing mode: @Rn (High Byte)
        #---------------------------------

        mov     #0x0001, r2        ;# Test 1: High Byte
        mov     #0x7225, &DMEM_208
        mov   #DMEM_209, r4
        mov     #0xaaaa, &DMEM_20A
        rra.b       @r4            ;# RRA.B ({mem04=0x7225}  => {mem04=0x3925, C=0})
        mov          r2, r6

        mov     #0x0001, r2        ;# Test 2: High Byte
        mov     #0x7325, &DMEM_20A
        mov   #DMEM_20B, r6
        mov     #0xaaaa, &DMEM_20C
        rra.b       @r6            ;# RRA.B ({mem05=0x7325}  => {mem05=0x3925, C=1})
        mov          r2, r8

        mov     #0x0000, r2        ;# Test 3: High Byte
        mov     #0x8225, &DMEM_20C
        mov   #DMEM_20D, r8
        mov     #0xaaaa, &DMEM_20E
        rra.b       @r8            ;# RRA.B ({mem06=0x8225}  => {mem06=0xc125, C=0})
        mov          r2, r10

        mov     #0x0000, r2        ;# Test 4: High Byte
        mov     #0x8325, &DMEM_20E
        mov   #DMEM_20F, r10
        mov     #0xaaaa, &DMEM_210
        rra.b      @r10            ;# RRA.B ({mem07=0x8325}  => {mem07=0xc125, C=1})
        mov          r2, r11

        mov     #0x9001, r15


        # Addressing mode: @Rn+ (Low Byte)
        #---------------------------------

        mov     #0x0001, r2        ;# Test 1: Low Byte
        mov     #0x2572, &DMEM_210
        mov   #DMEM_210, r4
        mov     #0xaaaa, &DMEM_212
        rra.b      @r4+            ;# RRA.B ({mem08=0x2582}  => {mem08=0x2539, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2: Low Byte
        mov     #0x2573, &DMEM_212
        mov   #DMEM_212, r6
        mov     #0xaaaa, &DMEM_214
        rra.b      @r6+            ;# RRA.B ({mem09=0x2583}  => {mem09=0x2539, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3: Low Byte
        mov     #0x2582, &DMEM_214
        mov   #DMEM_214, r8
        mov     #0xaaaa, &DMEM_216
        rra.b      @r8+            ;# RRA.B ({mem0a=0x2572}  => {mem0a=0x25c1, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4: Low Byte
        mov     #0x2583, &DMEM_216
        mov   #DMEM_216, r10
        mov     #0xaaaa, &DMEM_218
        rra.b     @r10+            ;# RRA.B ({mem0b=0x2573}  => {mem0b=0x25c1, C=1})
        mov          r2, r11

        mov     #0xA000, r15

        # Addressing mode: @Rn+ (High Byte)
        #-----------------------------------

        mov     #0x0001, r2        ;# Test 1: High Byte
        mov     #0x7225, &DMEM_218
        mov   #DMEM_219, r4
        mov     #0xaaaa, &DMEM_21A
        rra.b      @r4+            ;# RRA.B ({mem0c=0x7225}  => {mem0c=0x3925, C=0})
        mov          r2, r6

        mov     #0x0001, r2        ;# Test 2: High Byte
        mov     #0x7325, &DMEM_21A
        mov   #DMEM_21B, r6
        mov     #0xaaaa, &DMEM_21C
        rra.b      @r6+            ;# RRA.B ({mem0d=0x7325}  => {mem0d=0x3925, C=1})
        mov          r2, r8

        mov     #0x0000, r2        ;# Test 3: High Byte
        mov     #0x8225, &DMEM_21C
        mov   #DMEM_21D, r8
        mov     #0xaaaa, &DMEM_21E
        rra.b      @r8+            ;# RRA.B ({mem0e=0x8225}  => {mem0e=0xc125, C=0})
        mov          r2, r10

        mov     #0x0000, r2        ;# Test 4: High Byte
        mov     #0x8325, &DMEM_21E
        mov   #DMEM_21F, r10
        mov     #0xaaaa, &DMEM_220
        rra.b     @r10+            ;# RRA.B ({mem0f=0x8325}  => {mem0f=0xc125, C=1})
        mov          r2, r11

        mov     #0xA001, r15


        # Addressing mode: X(Rn) (Low Byte)
        #-----------------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x2572, &DMEM_220
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_222
        rra.b     32(r4)           ;# RRA ({mem10=0x2572}  => {mem10=0x2539, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x2573, &DMEM_222
        mov   #DMEM_200, r6
        mov     #0xaaaa, &DMEM_224
        rra.b     34(r6)           ;# RRA ({mem11=0x2573}  => {mem11=0x2539, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x2582, &DMEM_224
        mov   #DMEM_200, r8
        mov     #0xaaaa, &DMEM_226
        rra.b     36(r8)           ;# RRA ({mem12=0x2582}  => {mem12=0x25c1, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x2583, &DMEM_226
        mov   #DMEM_200, r10
        mov     #0xaaaa, &DMEM_228
        rra.b    38(r10)           ;# RRA ({mem13=0x2583}  => {mem13=0x25c1, C=1})
        mov          r2, r11

        mov     #0xB000, r15

        # Addressing mode: X(Rn) (High Byte)
        #------------------------------------

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7225, &DMEM_228
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_22A
        rra.b     41(r4)           ;# RRA ({mem14=0x7225}  => {mem14=0x3925, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7325, &DMEM_22A
        mov   #DMEM_200, r6
        mov     #0xaaaa, &DMEM_22C
        rra.b     43(r6)           ;# RRA ({mem15=0x7325}  => {mem15=0x3925, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8225, &DMEM_22C
        mov   #DMEM_200, r8
        mov     #0xaaaa, &DMEM_22E
        rra.b     45(r8)           ;# RRA ({mem16=0x8225}  => {mem16=0xc125, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8325, &DMEM_22E
        mov   #DMEM_200, r10
        mov     #0xaaaa, &DMEM_230
        rra.b    47(r10)           ;# RRA ({mem17=0x8325}  => {mem17=0xc125, C=1})
        mov          r2, r11

        mov     #0xB001, r15


        # Addressing mode: EDE (Low Byte)
        #---------------------------------
.set   EDE_230,  DMEM_230
.set   EDE_232,  DMEM_232
.set   EDE_234,  DMEM_234
.set   EDE_236,  DMEM_236

        mov     #0x0001, r2        ;# Test 1
        mov     #0x2572, &DMEM_230
        mov     #0xaaaa, &DMEM_232
        rra.b   EDE_230            ;# RRA ({mem18=0x2572}  => {mem18=0x2539, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x2573, &DMEM_232
        mov     #0xaaaa, &DMEM_234
        rra.b   EDE_232            ;# RRA ({mem19=0x2573}  => {mem19=0x2539, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x2582, &DMEM_234
        mov     #0xaaaa, &DMEM_236
        rra.b   EDE_234            ;# RRA ({mem1a=0x2582}  => {mem1a=0x25c1, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x2583, &DMEM_236
        mov     #0xaaaa, &DMEM_238
        rra.b   EDE_236            ;# RRA ({mem1b=0x2583}  => {mem1b=0x25c1, C=1})
        mov          r2, r11

        mov     #0xC000, r15

        # Addressing mode: EDE (High Byte)
        #----------------------------------
.set   EDE_239,  DMEM_239
.set   EDE_23B,  DMEM_23B
.set   EDE_23D,  DMEM_23D
.set   EDE_23F,  DMEM_23F

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7225, &DMEM_238
        mov     #0xaaaa, &DMEM_23A
        rra.b   EDE_239            ;# RRA ({mem1c=0x7225}  => {mem1c=0x3925, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7325, &DMEM_23A
        mov     #0xaaaa, &DMEM_23C
        rra.b   EDE_23B            ;# RRA ({mem1d=0x7325}  => {mem1d=0x3925, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8225, &DMEM_23C
        mov     #0xaaaa, &DMEM_23E
        rra.b   EDE_23D            ;# RRA ({mem1e=0x8225}  => {mem1e=0xc125, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8325, &DMEM_23E
        mov     #0xaaaa, &DMEM_240
        rra.b   EDE_23F            ;# RRA ({mem1f=0x8325}  => {mem1f=0xc125, C=1})
        mov          r2, r11

        mov     #0xC001, r15


        # Addressing mode: &EDE (Low Byte)
        #----------------------------------
.set   aEDE_240,  DMEM_240
.set   aEDE_242,  DMEM_242
.set   aEDE_244,  DMEM_244
.set   aEDE_246,  DMEM_246

        mov     #0x0001, r2        ;# Test 1
        mov     #0x2572, &DMEM_240
        mov     #0xaaaa, &DMEM_242
        rra.b &aEDE_240            ;# RRA ({mem20=0x2572}  => {mem20=0x2539, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x2573, &DMEM_242
        mov     #0xaaaa, &DMEM_244
        rra.b &aEDE_242            ;# RRA ({mem21=0x2573}  => {mem21=0x2539, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x2582, &DMEM_244
        mov     #0xaaaa, &DMEM_246
        rra.b &aEDE_244            ;# RRA ({mem22=0x2582}  => {mem22=0x25c1, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x2583, &DMEM_246
        mov     #0xaaaa, &DMEM_248
        rra.b &aEDE_246            ;# RRA ({mem23=0x2583}  => {mem23=0x25c1, C=1})
        mov          r2, r11

        mov     #0xD000, r15

        # Addressing mode: &EDE (High Byte)
        #-----------------------------------
.set   aEDE_249,  DMEM_249
.set   aEDE_24B,  DMEM_24B
.set   aEDE_24D,  DMEM_24D
.set   aEDE_24F,  DMEM_24F

        mov     #0x0001, r2        ;# Test 1
        mov     #0x7225, &DMEM_248
        mov     #0xaaaa, &DMEM_24A
        rra.b &aEDE_249            ;# RRA ({mem24=0x7225}  => {mem24=0x3925, C=0})
        mov          r2, r5

        mov     #0x0001, r2        ;# Test 2
        mov     #0x7325, &DMEM_24A
        mov     #0xaaaa, &DMEM_24C
        rra.b &aEDE_24B            ;# RRA ({mem25=0x7325}  => {mem25=0x3925, C=1})
        mov          r2, r7

        mov     #0x0000, r2        ;# Test 3
        mov     #0x8225, &DMEM_24C
        mov     #0xaaaa, &DMEM_24E
        rra.b &aEDE_24D            ;# RRA ({mem26=0x8225}  => {mem26=0xc125, C=0})
        mov          r2, r9

        mov     #0x0000, r2        ;# Test 4
        mov     #0x8325, &DMEM_24E
        mov     #0xaaaa, &DMEM_250
        rra.b &aEDE_24F            ;# RRA ({mem27=0x8325}  => {mem27=0xc125, C=1})
        mov          r2, r11

        mov     #0xD001, r15



        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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