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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_swpb.s43] - Rev 155
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* SINGLE-OPERAND ARITHMETIC: SWPB INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SWPB instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */
/*===========================================================================*/
.include "pmem_defs.asm"
.global main
main:
/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
# Addressing mode: Rn
#------------------------
mov #0x0102, r2 ;# Test 1
mov #0x7524, r4
swpb r4 ;# SWPB (r4=0x7524 => r4=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, r6
swpb r6 ;# SWPB (r6=0x1cb6 => r6=0xb61c)
mov r2, r7
mov #0x1000, r15
# Addressing mode: @Rn
#------------------------
mov #0x0102, r2 ;# Test 1
mov #0x7524, &DMEM_200
mov #DMEM_200, r4
mov #0xaaaa, &DMEM_202
swpb @r4 ;# SWPB (mem00=0x7524 => {mem00=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, &DMEM_202
mov #DMEM_202, r6
mov #0xaaaa, &DMEM_204
swpb @r6 ;# SWPB (mem01=0x1cb6 => {mem01=0xb61c)
mov r2, r7
mov #0x2000, r15
# Addressing mode: @Rn+
#------------------------
mov #0x0102, r2 ;# Test 1
mov #0x7524, &DMEM_208
mov #DMEM_208, r4
mov #0xaaaa, &DMEM_20A
swpb @r4+ ;# SWPB (mem04=0x7524 => {mem04=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, &DMEM_20A
mov #DMEM_20A, r6
mov #0xaaaa, &DMEM_20C
swpb @r6+ ;# SWPB (mem05=0x1cb6 => {mem05=0xb61c)
mov r2, r7
mov #0x3000, r15
# Addressing mode: X(Rn)
#------------------------
mov #0x0102, r2 ;# Test 1
mov #0x7524, &DMEM_210
mov #DMEM_200, r4
mov #0xaaaa, &DMEM_212
swpb 16(r4) ;# SWPB (mem08=0x7524 => {mem08=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, &DMEM_212
mov #DMEM_200, r6
mov #0xaaaa, &DMEM_214
swpb 18(r6) ;# SWPB (mem09=0x1cb6 => {mem09=0xb61c)
mov r2, r7
mov #0x4000, r15
# Addressing mode: EDE
#------------------------
.set EDE_218, DMEM_218
.set EDE_21A, DMEM_21A
.set EDE_21C, DMEM_21C
.set EDE_21E, DMEM_21E
mov #0x0102, r2 ;# Test 1
mov #0x7524, &DMEM_218
mov #0xaaaa, &DMEM_21A
swpb EDE_218+PMEM_LENGTH ;# SWPB (mem0c=0x7524 => {mem0c=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, &DMEM_21A
mov #0xaaaa, &DMEM_21C
swpb EDE_21A+PMEM_LENGTH ;# SWPB (mem0d=0x1cb6 => {mem0d=0xb61c)
mov r2, r7
mov #0x5000, r15
# Addressing mode: &EDE
#------------------------
.set aEDE_220, DMEM_220
.set aEDE_222, DMEM_222
.set aEDE_224, DMEM_224
.set aEDE_226, DMEM_226
mov #0x0102, r2 ;# Test 1
mov #0x7524, &DMEM_220
mov #0xaaaa, &DMEM_222
swpb &aEDE_220 ;# SWPB (mem10=0x7524 => {mem10=0x2475)
mov r2, r5
mov #0x0005, r2 ;# Test 2
mov #0x1cb6, &DMEM_222
mov #0xaaaa, &DMEM_224
swpb &aEDE_222 ;# SWPB (mem11=0x1cb6 => {mem11=0xb61c)
mov r2, r7
mov #0x6000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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