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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_sxt.s43] - Rev 44
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */
/*---------------------------------------------------------------------------*/
/* Test the SXT instruction. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
.global main
main:
/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
# Addressing mode: Rn
#------------------------
mov #0x0100, r2 ;# Test 1
mov #0x7524, r4
sxt r4 ;# SXT (r4=0x7524 => r4=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, r6
sxt r6 ;# SXT (r6=0x1cb6 => r6=0xffb6)
mov r2, r7
mov #0x1000, r15
# Addressing mode: @Rn
#------------------------
mov #0x0100, r2 ;# Test 1
mov #0x7524, &0x0200
mov #0x0200, r4
mov #0xaaaa, &0x0202
sxt @r4 ;# SXT (mem00=0x7524 => {mem00=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, &0x0202
mov #0x0202, r6
mov #0xaaaa, &0x0204
sxt @r6 ;# SXT (mem01=0x1cb6 => {mem01=0xffb6)
mov r2, r7
mov #0x2000, r15
# Addressing mode: @Rn+
#------------------------
mov #0x0100, r2 ;# Test 1
mov #0x7524, &0x0208
mov #0x0208, r4
mov #0xaaaa, &0x020A
sxt @r4+ ;# SXT (mem04=0x7524 => {mem04=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, &0x020A
mov #0x020A, r6
mov #0xaaaa, &0x020C
sxt @r6+ ;# SXT (mem05=0x1cb6 => {mem05=0xffb6)
mov r2, r7
mov #0x3000, r15
# Addressing mode: X(Rn)
#------------------------
mov #0x0100, r2 ;# Test 1
mov #0x7524, &0x0210
mov #0x0200, r4
mov #0xaaaa, &0x0212
sxt 16(r4) ;# SXT (mem08=0x7524 => {mem08=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, &0x0212
mov #0x0200, r6
mov #0xaaaa, &0x0214
sxt 18(r6) ;# SXT (mem09=0x1cb6 => {mem09=0xffb6)
mov r2, r7
mov #0x4000, r15
# Addressing mode: EDE
#------------------------
.set EDE_218, (__data_start+0x0018)
.set EDE_21A, (__data_start+0x001A)
.set EDE_21C, (__data_start+0x001C)
.set EDE_21E, (__data_start+0x001E)
mov #0x0100, r2 ;# Test 1
mov #0x7524, &0x0218
mov #0xaaaa, &0x021A
sxt EDE_218 ;# SXT (mem0c=0x7524 => {mem0c=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, &0x021A
mov #0xaaaa, &0x021C
sxt EDE_21A ;# SXT (mem0d=0x1cb6 => {mem0d=0xffb6)
mov r2, r7
mov #0x5000, r15
# Addressing mode: &EDE
#------------------------
.set aEDE_220, 0x0220
.set aEDE_222, 0x0222
.set aEDE_224, 0x0224
.set aEDE_226, 0x0226
mov #0x0100, r2 ;# Test 1
mov #0x7524, &0x0220
mov #0xaaaa, &0x0222
sxt &aEDE_220 ;# SXT (mem10=0x7524 => {mem10=0x0024)
mov r2, r5
mov #0x0100, r2 ;# Test 2
mov #0x1cb6, &0x0222
mov #0xaaaa, &0x0224
sxt &aEDE_222 ;# SXT (mem11=0x1cb6 => {mem11=0xffb6)
mov r2, r7
mov #0x6000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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