Subversion Repositories openmsp430

verilog work ../../../bench/verilog/tb_openMSP430.v
verilog work ../../../bench/verilog/ram.v
verilog work ../../../bench/verilog/io_cell.v
verilog work ../../../bench/verilog/msp_debug.v

verilog work ../../../rtl/verilog/openMSP430_defines.v
verilog work ../../../rtl/verilog/openMSP430.v
verilog work ../../../rtl/verilog/omsp_frontend.v
verilog work ../../../rtl/verilog/omsp_execution_unit.v
verilog work ../../../rtl/verilog/omsp_register_file.v
verilog work ../../../rtl/verilog/omsp_alu.v
verilog work ../../../rtl/verilog/omsp_sfr.v
verilog work ../../../rtl/verilog/omsp_clock_module.v
verilog work ../../../rtl/verilog/omsp_mem_backbone.v
verilog work ../../../rtl/verilog/omsp_watchdog.v
verilog work ../../../rtl/verilog/omsp_dbg.v
verilog work ../../../rtl/verilog/omsp_dbg_uart.v
verilog work ../../../rtl/verilog/omsp_dbg_i2c.v
verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v
verilog work ../../../rtl/verilog/omsp_multiplier.v
verilog work ../../../rtl/verilog/omsp_sync_reset.v
verilog work ../../../rtl/verilog/omsp_sync_cell.v
verilog work ../../../rtl/verilog/omsp_scan_mux.v
verilog work ../../../rtl/verilog/omsp_and_gate.v
verilog work ../../../rtl/verilog/omsp_wakeup_cell.v
verilog work ../../../rtl/verilog/omsp_clock_gate.v
verilog work ../../../rtl/verilog/omsp_clock_mux.v

verilog work ../../../rtl/verilog/periph/omsp_gpio.v
verilog work ../../../rtl/verilog/periph/omsp_timerA.v
verilog work ../../../rtl/verilog/periph/template_periph_8b.v
verilog work ../../../rtl/verilog/periph/template_periph_16b.v