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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_clkmux.s43] - Rev 120
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/*===========================================================================*//* Copyright (C) 2001 Authors *//* *//* This source file may be used and distributed without restriction provided *//* that this copyright statement is not removed from the file and that any *//* derivative work contains the original copyright notice and the associated *//* disclaimer. *//* *//* This source file is free software; you can redistribute it and/or modify *//* it under the terms of the GNU Lesser General Public License as published *//* by the Free Software Foundation; either version 2.1 of the License, or *//* (at your option) any later version. *//* *//* This source is distributed in the hope that it will be useful, but WITHOUT*//* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *//* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public *//* License for more details. *//* *//* You should have received a copy of the GNU Lesser General Public License *//* along with this source; if not, write to the Free Software Foundation, *//* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA *//* *//*===========================================================================*//* TIMER A *//*---------------------------------------------------------------------------*//* Test the timer A: *//* - Check the timer clock input mux. *//* *//* Author(s): *//* - Olivier Girard, olgirard@gmail.com *//* *//*---------------------------------------------------------------------------*//* $Rev: 111 $ *//* $LastChangedBy: olivier.girard $ *//* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ *//*===========================================================================*/.global main.set DMEM_BASE, (__data_start ).set DMEM_200, (__data_start+0x00).set DMEM_202, (__data_start+0x02).set DMEM_204, (__data_start+0x04).set DMEM_206, (__data_start+0x06).set DMEM_250, (__data_start+0x50).set BCSCTL1, 0x0057.set BCSCTL2, 0x0058.set TACTL, 0x0160.set TAR, 0x0170.set TACCTL0, 0x0162.set TACCR0, 0x0172.set TACCTL1, 0x0164.set TACCR1, 0x0174.set TACCTL2, 0x0166.set TACCR2, 0x0176.set TAIV, 0x012EWAIT_FUNC:dec r14jnz WAIT_FUNCretmain:mov #DMEM_250, r1 ; # Initialize stack pointermov #0x0000, &DMEM_200mov #0x0000, r15mov.b #0x00, &BCSCTL1 ; # ACLK /1mov.b #0x06, &BCSCTL2 ; # SMCLK = MCLK/8/* -------------- TIMER A TEST: INPUT MUX - TACLK ----------------- */mov #0x0000, &TACTLmov #0x0000, &TACCTL0dintmov #0x0000, &TACTLmov #0x0000, &TACCTL0mov #0x0000, &TARmov #0x0062, &TACTL ; # Continuous mode, /2mov #0x0001, r15mov #0x0100, r14call #WAIT_FUNCdintmov #0x0000, &DMEM_200mov #0x1000, r15/* -------------- TIMER A TEST: INPUT MUX - ACLK ----------------- */mov #0x0000, &TACTLmov #0x0000, &TACCTL0dintmov #0x0000, &TACTLmov #0x0000, &TACCTL0mov #0x0000, &TARmov #0x0162, &TACTL ; # Continuous mode, /2mov #0x1001, r15mov #0x0100, r14call #WAIT_FUNCdintmov #0x0000, &DMEM_200mov #0x2000, r15/* -------------- TIMER A TEST: INPUT MUX - SMCLK ----------------- */mov #0x0000, &TACTLmov #0x0000, &TACCTL0dintmov #0x0000, &TACTLmov #0x0000, &TACCTL0mov #0x0000, &TARmov #0x0262, &TACTL ; # Continuous mode, /2mov #0x2001, r15mov #0x0100, r14call #WAIT_FUNCdintmov #0x0000, &DMEM_200mov #0x3000, r15/* -------------- TIMER A TEST: INPUT MUX - INCLK ----------------- */mov #0x0000, &TACTLmov #0x0000, &TACCTL0dintmov #0x0000, &TACTLmov #0x0000, &TACCTL0mov #0x0000, &TARmov #0x0362, &TACTL ; # Continuous mode, /2mov #0x3001, r15mov #0x0100, r14call #WAIT_FUNCdintmov #0x0000, &DMEM_200mov #0x4000, r15/* ---------------------- END OF TEST --------------- */end_of_test:nopbr #0xffff/* ---------------------- INTERRUPT ROUTINES --------------- */TIMERA_CCR0_VECTOR:inc &DMEM_200retiTIMERA_TAIV_VECTOR:mov &TAR, &DMEM_204mov &TAIV, &DMEM_206reti/* ---------------------- INTERRUPT VECTORS --------------- */.section .vectors, "a".word end_of_test ; Interrupt 0 (lowest priority) <unused>.word end_of_test ; Interrupt 1 <unused>.word end_of_test ; Interrupt 2 <unused>.word end_of_test ; Interrupt 3 <unused>.word end_of_test ; Interrupt 4 <unused>.word end_of_test ; Interrupt 5 <unused>.word end_of_test ; Interrupt 6 <unused>.word end_of_test ; Interrupt 7 <unused>.word TIMERA_TAIV_VECTOR ; Interrupt 8 <unused>.word TIMERA_CCR0_VECTOR ; Interrupt 9 <unused>.word end_of_test ; Interrupt 10 Watchdog timer.word end_of_test ; Interrupt 11 <unused>.word end_of_test ; Interrupt 12 <unused>.word end_of_test ; Interrupt 13 <unused>.word end_of_test ; Interrupt 14 NMI.word main ; Interrupt 15 (highest priority) RESET
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