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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_modes.s43] - Rev 175
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* TIMER A */
/*---------------------------------------------------------------------------*/
/* Test the timer A: */
/* - Check RD/WR register access. */
/* - Check the clock divider. */
/* - Check the timer modes. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 141 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $ */
/*===========================================================================*/
.include "pmem_defs.asm"
.global main
WAIT_FUNC:
dec r14
jnz WAIT_FUNC
ret
main:
mov #DMEM_250, r1 ; # Initialize stack pointer
mov #0x0000, &DMEM_200
/* -------------- TIMER A TEST: RD/WR ACCESS --------------- */
mov #0xaaaa, &TACTL ; # TACTL
mov &TACTL, &DMEM_200
mov #0x5555, &TACTL
mov &TACTL, &DMEM_202
mov #0x0000, &TACTL
mov &TACTL, &DMEM_204
mov #0x0000, &TACTL
mov &TACTL, &DMEM_206
mov #0xaaaa, &TAR ; # TAR
mov &TAR, &DMEM_208
mov #0x5555, &TAR
mov &TAR, &DMEM_20A
mov #0x0000, &TAR
mov &TAR, &DMEM_20C
mov #0xaaaa, &TACCTL0 ; # TACCTL0
mov &TACCTL0, &DMEM_210
mov #0x5555, &TACCTL0
mov &TACCTL0, &DMEM_212
mov #0x0000, &TACCTL0
mov &TACCTL0, &DMEM_214
mov #0xaaaa, &TACCR0 ; # TACCR0
mov &TACCR0, &DMEM_216
mov #0x5555, &TACCR0
mov &TACCR0, &DMEM_218
mov #0x0000, &TACCR0
mov &TACCR0, &DMEM_21A
mov #0xaaaa, &TACCTL1 ; # TACCTL1
mov &TACCTL1, &DMEM_220
mov #0x5555, &TACCTL1
mov &TACCTL1, &DMEM_222
mov #0x0000, &TACCTL1
mov &TACCTL1, &DMEM_224
mov #0xaaaa, &TACCR1 ; # TACCR1
mov &TACCR1, &DMEM_226
mov #0x5555, &TACCR1
mov &TACCR1, &DMEM_228
mov #0x0000, &TACCR1
mov &TACCR1, &DMEM_22A
mov #0xaaaa, &TACCTL2 ; # TACCTL2
mov &TACCTL2, &DMEM_230
mov #0x5555, &TACCTL2
mov &TACCTL2, &DMEM_232
mov #0x0000, &TACCTL2
mov &TACCTL2, &DMEM_234
mov #0xaaaa, &TACCR2 ; # TACCR2
mov &TACCR2, &DMEM_236
mov #0x5555, &TACCR2
mov &TACCR2, &DMEM_238
mov #0x0000, &TACCR2
mov &TACCR2, &DMEM_23A
mov #0xaaaa, &TAIV ; # TAIV
mov &TAIV, &DMEM_240
mov #0x5555, &TAIV
mov &TAIV, &DMEM_242
mov #0x0000, &TAIV
mov &TAIV, &DMEM_244
mov #0x1000, r15
/* -------------- TIMER A TEST: INPUT DIVIDER --------------- */
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
eint
mov #0x0200, &TACTL
mov #0x0020, &TACCR0
mov #0x0216, &TACTL ; # /1
mov #0x0001, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0010, &TACCR0
mov #0x0256, &TACTL ; # /2
mov #0x0002, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0008, &TACCR0
mov #0x0296, &TACTL ; # /4
mov #0x0003, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0004, &TACCR0
mov #0x02D6, &TACTL ; # /8
mov #0x0004, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
dint
mov #0x0000, &DMEM_200
mov #0x2000, r15
/* -------------- TIMER A TEST: UP MODE ----------------- */
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
eint
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
mov #0x0256, &TACTL
mov #0x0001, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
mov #0x0256, &TACTL
mov #0x0002, &DMEM_200
mov #0x0020, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x0012, &TACCR0 ; # Check timing for period = 0x12 +1
mov #0x0254, &TACTL
mov #0x0010, &TACCTL0
mov #0x0003, &DMEM_200
mov #0x0010, r14
call #WAIT_FUNC
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x001E, &TACCR0 ; # Check timing for period = 0x1E +1
mov #0x0254, &TACTL
mov #0x0010, &TACCTL0
mov #0x0004, &DMEM_200
mov #0x0020, r14
call #WAIT_FUNC
dint
mov #0x0000, &DMEM_200
mov #0x3000, r15
/* -------------- TIMER A TEST: CONTINUOUS MODES ----------------- */
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
eint
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0xfff0, &TAR ; # Continuous mode
mov #0x0262, &TACTL
mov #0x0001, &DMEM_200
mov #0x0020, r14
call #WAIT_FUNC
dint
mov #0x0000, &DMEM_200
mov #0x4000, r15
/* -------------- TIMER A TEST: UP-DOWN MODE ----------------- */
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
eint
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x0031, &TACCR0 ; # Up-Down mode - timing 1
mov #0x0000, &TAR
mov #0x0236, &TACTL
mov #0x0010, &TACCTL0
mov #0x0001, &DMEM_200
mov #0x0050, r14
call #WAIT_FUNC
mov #0x0002, &DMEM_200
dint
mov #0x0200, &TACTL
mov #0x0000, &TACCTL0
mov #0x0000, &DMEM_200
mov #0x5000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT ROUTINES --------------- */
TIMERA_CCR0_VECTOR:
mov &TAR, &DMEM_204
reti
TIMERA_TAIV_VECTOR:
mov &TAR, &DMEM_202
bic #0x0001, &TACTL
reti
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word TIMERA_TAIV_VECTOR ; Interrupt 8 <unused>
.word TIMERA_CCR0_VECTOR ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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