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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_16b.s43] - Rev 79
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/*===========================================================================*//* Copyright (C) 2001 Authors *//* *//* This source file may be used and distributed without restriction provided *//* that this copyright statement is not removed from the file and that any *//* derivative work contains the original copyright notice and the associated *//* disclaimer. *//* *//* This source file is free software; you can redistribute it and/or modify *//* it under the terms of the GNU Lesser General Public License as published *//* by the Free Software Foundation; either version 2.1 of the License, or *//* (at your option) any later version. *//* *//* This source is distributed in the hope that it will be useful, but WITHOUT*//* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or *//* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public *//* License for more details. *//* *//* You should have received a copy of the GNU Lesser General Public License *//* along with this source; if not, write to the Free Software Foundation, *//* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA *//* *//*===========================================================================*//* 16 BIT PERIPHERAL TEMPLATE *//*---------------------------------------------------------------------------*//* Test the 16 bit peripheral template: *//* - Read/Write register access. *//* *//* Author(s): *//* - Olivier Girard, olgirard@gmail.com *//* *//*---------------------------------------------------------------------------*//* $Rev: 19 $ *//* $LastChangedBy: olivier.girard $ *//* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ *//*===========================================================================*/.global main.set CNTRL1, 0x0190.set CNTRL2, 0x0192.set CNTRL3, 0x0194.set CNTRL4, 0x0196main:/* -------------- TEST RD/WR REGISTER ACCESS --------------- */mov #0x5555, &CNTRL1 ; CNTRL1mov &CNTRL1, &0x0200mov #0xaaaa, &CNTRL1mov &CNTRL1, &0x0202mov #0xaaaa, &CNTRL2 ; CNTRL2mov &CNTRL2, &0x0204mov #0x5555, &CNTRL2mov &CNTRL2, &0x0206mov #0x55aa, &CNTRL3 ; CNTRL3mov &CNTRL3, &0x0208mov #0xaa55, &CNTRL3mov &CNTRL3, &0x020Amov #0xaa55, &CNTRL4 ; CNTRL4mov &CNTRL4, &0x020Cmov #0x55aa, &CNTRL4mov &CNTRL4, &0x020Emov #0x0001, r15/* ---------------------- END OF TEST --------------- */end_of_test:nopbr #0xffff/* ---------------------- INTERRUPT VECTORS --------------- */.section .vectors, "a".word end_of_test ; Interrupt 0 (lowest priority) <unused>.word end_of_test ; Interrupt 1 <unused>.word end_of_test ; Interrupt 2 <unused>.word end_of_test ; Interrupt 3 <unused>.word end_of_test ; Interrupt 4 <unused>.word end_of_test ; Interrupt 5 <unused>.word end_of_test ; Interrupt 6 <unused>.word end_of_test ; Interrupt 7 <unused>.word end_of_test ; Interrupt 8 <unused>.word end_of_test ; Interrupt 9 <unused>.word end_of_test ; Interrupt 10 Watchdog timer.word end_of_test ; Interrupt 11 <unused>.word end_of_test ; Interrupt 12 <unused>.word end_of_test ; Interrupt 13 <unused>.word end_of_test ; Interrupt 14 NMI.word main ; Interrupt 15 (highest priority) RESET
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