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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Rev 111
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Clock source selection. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
/*===========================================================================*/
.global main
.set DMEM_BASE, (__data_start )
.set DMEM_200, (__data_start+0x00)
.set DMEM_250, (__data_start+0x50)
.set BCSCTL1, 0x0057
.set BCSCTL2, 0x0058
.set IE1, 0x0000
.set IFG1, 0x0002
.set WDTCTL, 0x0120
WAIT_FUNC:
dec r14
jnz WAIT_FUNC
ret
main:
/* ------- WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2 ------ */
mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov.b #0x02, &BCSCTL2 ;# SMCLK = MCLK/2
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
mov #0x0001, r15
mov #0x0170, r14
call #WAIT_FUNC
mov #0x1000, r15
/* ------- WATCHDOG TEST INTERVAL MODE /64 - ACLK ------ */
mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov.b #0x00, &BCSCTL1 ;# ACLK = LFXTCLK/1
mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 & clear counter
mov #0x1001, r15
mov #0x1000, r14
call #WAIT_FUNC
mov #0x2000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT ROUTINES --------------- */
WDOG_VECTOR:
xor #0x0001, r5 ; # Toggle r5[0] for testbench stimulus check
reti
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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