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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Rev 110
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/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Interval timer mode. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
.global main
.set IE1, 0x0000
.set IFG1, 0x0002
.set WDTCTL, 0x0120
main:
/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
mov &WDTCTL, r4
mov #0x5aff, &WDTCTL
mov &WDTCTL, r5
mov #0x5a55, &WDTCTL
mov &WDTCTL, r6
mov #0x5aaa, &WDTCTL
mov &WDTCTL, r7
mov #0x5a00, &WDTCTL
mov &WDTCTL, r8
mov #0x1000, r15
/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
mov #0x0000, r4
mov #0x0001, r5
wait_loop_64:
inc r4
cmp #0x3401, r5
jne wait_loop_64
mov #0x2000, r15
bic.b #0x01, &IE1 ;# Disable watchdog interrupt
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
mov #0x0010, r4
mov #0x0002, r5
wait_loop_64_no_irq:
dec r4
cmp #0x0000, r4
jne wait_loop_64_no_irq
mov &IFG1, r6
mov r4, r7
bic.b #0x01, &IFG1 ;# Clear flag
mov &IFG1, r8
mov #0x2001, r15
mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold
mov #0x0020, r4
mov #0x0022, r5
wait_loop_64_no_irq_hold:
dec r4
cmp #0x0000, r4
jne wait_loop_64_no_irq_hold
mov &IFG1, r6
mov r4, r7
mov #0x2002, r15
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear
mov #0x0033, r4
mov #0x000C, r5
wait_loop_64_no_irq_clear1:
dec r5
cmp #0x0000, r5
jne wait_loop_64_no_irq_clear1
mov #0x5a1b, &WDTCTL ;# Clear counter
mov &IFG1, r6
mov #0x000C, r5
wait_loop_64_no_irq_clear2:
dec r5
cmp #0x0000, r5
jne wait_loop_64_no_irq_clear2
mov &IFG1, r7 ;# Don't Clear counter
mov #0x000C, r5
wait_loop_64_no_irq_clear3:
dec r5
cmp #0x0000, r5
jne wait_loop_64_no_irq_clear3
mov &IFG1, r8
bic.b #0x01, &IFG1 ;# Clear flag
mov #0x2003, r15
/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter
mov #0x0000, r4
mov #0x0003, r5
wait_loop_512:
inc r4
cmp #0x3403, r5
jne wait_loop_512
mov #0x3000, r15
/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter
mov #0x0000, r4
mov #0x0004, r5
wait_loop_8192:
inc r4
cmp #0x3404, r5
jne wait_loop_8192
mov #0x4000, r15
/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
eint
bis.b #0x01, &IE1
mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter
mov #0x0000, r4
mov #0x0005, r5
wait_loop_32768:
inc r4
cmp #0x3405, r5
jne wait_loop_32768
mov #0x5000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
/* ---------------------- INTERRUPT ROUTINES --------------- */
WDOG_VECTOR:
bis #0x3400, r5
mov &IFG1, r6
mov r4, r7
reti
/* ---------------------- INTERRUPT VECTORS --------------- */
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word end_of_test ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word WDOG_VECTOR ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
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