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Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.log] - Rev 208
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###################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 59.496Frequency (MHz): 16.808Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 56.596External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 65.840Input to OutputMin Delay (ns): 0.000Max Delay (ns): 62.940====================================================================================Compile report:===============CORE Used: 3585Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3106 | 3106SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.520Frequency (MHz): 18.012Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.193External Hold (ns): 0.486Min Clock-To-Out (ns): 3.058Max Clock-To-Out (ns): 64.779Input to OutputMin Delay (ns): 2.046Max Delay (ns): 60.452====================================================================================Compile report:===============CORE Used: 3635Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3156 | 3156SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 44.550Frequency (MHz): 22.447Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 41.682External Hold (ns): 0.248Min Clock-To-Out (ns): 3.318Max Clock-To-Out (ns): 51.566Input to OutputMin Delay (ns): 2.088Max Delay (ns): 48.698====================================================================================Compile report:===============CORE Used: 3556Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3077 | 3077SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 69.886Frequency (MHz): 14.309Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.083External Hold (ns): 0.765Min Clock-To-Out (ns): 7.615Max Clock-To-Out (ns): 75.891Input to OutputMin Delay (ns): 4.971Max Delay (ns): 71.088====================================================================================Compile report:===============CORE Used: 3549Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3069 | 3069SEQ | 480 | 480====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.165Frequency (MHz): 18.127Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.175External Hold (ns): 0.935Min Clock-To-Out (ns): 6.100Max Clock-To-Out (ns): 62.347Input to OutputMin Delay (ns): 4.213Max Delay (ns): 58.357====================================================================================Compile report:===============CORE Used: 3535Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3056 | 3056SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 60.713Frequency (MHz): 16.471Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 58.080External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 67.811Input to OutputMin Delay (ns): 0.000Max Delay (ns): 65.178====================================================================================Compile report:===============CORE Used: 3585Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3106 | 3106SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.458Frequency (MHz): 18.032Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 50.559External Hold (ns): 0.424Min Clock-To-Out (ns): 2.941Max Clock-To-Out (ns): 64.709Input to OutputMin Delay (ns): 1.904Max Delay (ns): 59.812====================================================================================Compile report:===============CORE Used: 3635Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3156 | 3156SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 43.859Frequency (MHz): 22.800Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 41.325External Hold (ns): 0.349Min Clock-To-Out (ns): 3.018Max Clock-To-Out (ns): 48.521Input to OutputMin Delay (ns): 1.893Max Delay (ns): 45.987====================================================================================Compile report:===============CORE Used: 3556Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3077 | 3077SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 60.059Frequency (MHz): 16.650Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 57.164External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 68.807Input to OutputMin Delay (ns): 0.000Max Delay (ns): 65.912====================================================================================Compile report:===============CORE Used: 3585Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3106 | 3106SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.859Frequency (MHz): 17.902Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 49.060External Hold (ns): 0.991Min Clock-To-Out (ns): 3.083Max Clock-To-Out (ns): 62.333Input to OutputMin Delay (ns): 2.212Max Delay (ns): 55.534====================================================================================Compile report:===============CORE Used: 3635Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3156 | 3156SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 44.843Frequency (MHz): 22.300Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 40.185External Hold (ns): 1.018Min Clock-To-Out (ns): 2.963Max Clock-To-Out (ns): 51.927Input to OutputMin Delay (ns): 2.260Max Delay (ns): 47.269====================================================================================Compile report:===============CORE Used: 3556Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3077 | 3077SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 71.404Frequency (MHz): 14.005Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.180External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 79.196Input to OutputMin Delay (ns): 0.000Max Delay (ns): 72.972====================================================================================Compile report:===============CORE Used: 3646Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 3167 | 3167SEQ | 479 | 479====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 71.522Frequency (MHz): 13.982Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 62.333External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 71.649Input to OutputMin Delay (ns): 0.000Max Delay (ns): 70.065====================================================================================Compile report:===============CORE Used: 4884Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4261 | 4261SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.799Frequency (MHz): 17.921Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 55.847External Hold (ns): 0.430Min Clock-To-Out (ns): 3.127Max Clock-To-Out (ns): 62.868Input to OutputMin Delay (ns): 2.070Max Delay (ns): 62.916====================================================================================Compile report:===============CORE Used: 4742Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4118 | 4118SEQ | 624 | 624====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 46.678Frequency (MHz): 21.423Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 45.726External Hold (ns): 0.184Min Clock-To-Out (ns): 3.121Max Clock-To-Out (ns): 52.569Input to OutputMin Delay (ns): 2.125Max Delay (ns): 51.617====================================================================================Compile report:===============CORE Used: 4811Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4188 | 4188SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 66.074Frequency (MHz): 15.135Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.604External Hold (ns): 0.636Min Clock-To-Out (ns): 6.321Max Clock-To-Out (ns): 74.907Input to OutputMin Delay (ns): 4.750Max Delay (ns): 75.465====================================================================================Compile report:===============CORE Used: 4774Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4151 | 4151SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 62.880Frequency (MHz): 15.903Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 58.918External Hold (ns): 0.501Min Clock-To-Out (ns): 5.767Max Clock-To-Out (ns): 68.704Input to OutputMin Delay (ns): 4.032Max Delay (ns): 66.092====================================================================================Compile report:===============CORE Used: 4776Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4153 | 4153SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 66.554Frequency (MHz): 15.025Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 61.743External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 72.194Input to OutputMin Delay (ns): 0.000Max Delay (ns): 70.797====================================================================================Compile report:===============CORE Used: 4884Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4261 | 4261SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 54.375Frequency (MHz): 18.391Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 54.649External Hold (ns): 0.420Min Clock-To-Out (ns): 2.827Max Clock-To-Out (ns): 59.461Input to OutputMin Delay (ns): 1.902Max Delay (ns): 59.735====================================================================================Compile report:===============CORE Used: 4742Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4118 | 4118SEQ | 624 | 624====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 46.154Frequency (MHz): 21.667Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 46.484External Hold (ns): 0.353Min Clock-To-Out (ns): 3.003Max Clock-To-Out (ns): 51.186Input to OutputMin Delay (ns): 1.940Max Delay (ns): 51.965====================================================================================Compile report:===============CORE Used: 4811Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4188 | 4188SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 70.208Frequency (MHz): 14.243Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 60.252External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 69.971Input to OutputMin Delay (ns): 0.000Max Delay (ns): 68.565====================================================================================Compile report:===============CORE Used: 4884Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4261 | 4261SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 56.209Frequency (MHz): 17.791Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 54.735External Hold (ns): 0.685Min Clock-To-Out (ns): 2.951Max Clock-To-Out (ns): 61.627Input to OutputMin Delay (ns): 2.212Max Delay (ns): 60.153====================================================================================Compile report:===============CORE Used: 4742Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4118 | 4118SEQ | 624 | 624====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 48.594Frequency (MHz): 20.579Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 49.120External Hold (ns): 1.041Min Clock-To-Out (ns): 2.988Max Clock-To-Out (ns): 53.864Input to OutputMin Delay (ns): 2.262Max Delay (ns): 54.390====================================================================================Compile report:===============CORE Used: 4811Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4188 | 4188SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 73.462Frequency (MHz): 13.612Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 64.585External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 73.620Input to OutputMin Delay (ns): 0.000Max Delay (ns): 70.771====================================================================================Compile report:===============CORE Used: 4857Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4234 | 4234SEQ | 623 | 623====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 61.636Frequency (MHz): 16.224Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 57.137External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 67.618Input to OutputMin Delay (ns): 0.000Max Delay (ns): 63.463====================================================================================Compile report:===============CORE Used: 5014Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4348 | 4348SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 62.374Frequency (MHz): 16.032Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 52.661External Hold (ns): 0.369Min Clock-To-Out (ns): 3.057Max Clock-To-Out (ns): 60.319Input to OutputMin Delay (ns): 2.079Max Delay (ns): 57.466====================================================================================Compile report:===============CORE Used: 5004Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4337 | 4337SEQ | 667 | 667====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 47.073Frequency (MHz): 21.244Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 46.714External Hold (ns): 0.437Min Clock-To-Out (ns): 3.315Max Clock-To-Out (ns): 52.799Input to OutputMin Delay (ns): 2.109Max Delay (ns): 52.440====================================================================================Compile report:===============CORE Used: 5002Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4336 | 4336SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 69.350Frequency (MHz): 14.420Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 66.678External Hold (ns): 1.139Min Clock-To-Out (ns): 6.759Max Clock-To-Out (ns): 73.782Input to OutputMin Delay (ns): 4.757Max Delay (ns): 72.203====================================================================================Compile report:===============CORE Used: 5012Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4345 | 4345SEQ | 667 | 667====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 54.514Frequency (MHz): 18.344Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 52.044External Hold (ns): 0.934Min Clock-To-Out (ns): 5.679Max Clock-To-Out (ns): 62.000Input to OutputMin Delay (ns): 4.032Max Delay (ns): 58.639====================================================================================Compile report:===============CORE Used: 5032Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4366 | 4366SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 60.421Frequency (MHz): 16.551Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 58.594External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 69.078Input to OutputMin Delay (ns): 0.000Max Delay (ns): 67.251====================================================================================Compile report:===============CORE Used: 5014Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4348 | 4348SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 54.338Frequency (MHz): 18.403Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.572External Hold (ns): 0.643Min Clock-To-Out (ns): 2.515Max Clock-To-Out (ns): 58.728Input to OutputMin Delay (ns): 1.854Max Delay (ns): 55.962====================================================================================Compile report:===============CORE Used: 5004Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4337 | 4337SEQ | 667 | 667====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 47.071Frequency (MHz): 21.245Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 47.553External Hold (ns): 0.528Min Clock-To-Out (ns): 2.730Max Clock-To-Out (ns): 50.373Input to OutputMin Delay (ns): 1.940Max Delay (ns): 50.855====================================================================================Compile report:===============CORE Used: 5002Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4336 | 4336SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 64.110Frequency (MHz): 15.598Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 62.268External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 75.575Input to OutputMin Delay (ns): 0.000Max Delay (ns): 73.733====================================================================================Compile report:===============CORE Used: 5014Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4348 | 4348SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.995Frequency (MHz): 17.859Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 53.992External Hold (ns): 0.998Min Clock-To-Out (ns): 2.999Max Clock-To-Out (ns): 62.056Input to OutputMin Delay (ns): 2.211Max Delay (ns): 60.053====================================================================================Compile report:===============CORE Used: 5004Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4337 | 4337SEQ | 667 | 667====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 49.346Frequency (MHz): 20.265Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 46.472External Hold (ns): 1.023Min Clock-To-Out (ns): 2.997Max Clock-To-Out (ns): 52.969Input to OutputMin Delay (ns): 2.297Max Delay (ns): 53.522====================================================================================Compile report:===============CORE Used: 5002Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4336 | 4336SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 72.222Frequency (MHz): 13.846Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 66.967External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 79.167Input to OutputMin Delay (ns): 0.000Max Delay (ns): 73.912====================================================================================Compile report:===============CORE Used: 5016Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4350 | 4350SEQ | 666 | 666====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 60.040Frequency (MHz): 16.656Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 56.383External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 67.070Input to OutputMin Delay (ns): 0.000Max Delay (ns): 63.561====================================================================================Compile report:===============CORE Used: 5263Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4554 | 4554SEQ | 709 | 709====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 52.542Frequency (MHz): 19.032Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.724External Hold (ns): 0.390Min Clock-To-Out (ns): 3.241Max Clock-To-Out (ns): 60.476Input to OutputMin Delay (ns): 2.048Max Delay (ns): 59.658====================================================================================Compile report:===============CORE Used: 5246Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4538 | 4538SEQ | 708 | 708====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 41.647Frequency (MHz): 24.011Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 40.940External Hold (ns): 0.393Min Clock-To-Out (ns): 3.373Max Clock-To-Out (ns): 49.023Input to OutputMin Delay (ns): 2.162Max Delay (ns): 48.316====================================================================================Compile report:===============CORE Used: 5210Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4503 | 4503SEQ | 707 | 707====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 67.866Frequency (MHz): 14.735Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 67.341External Hold (ns): 0.633Min Clock-To-Out (ns): 6.638Max Clock-To-Out (ns): 77.183Input to OutputMin Delay (ns): 4.759Max Delay (ns): 76.658====================================================================================Compile report:===============CORE Used: 5183Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4474 | 4474SEQ | 709 | 709====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 58.347Frequency (MHz): 17.139Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 53.616External Hold (ns): 0.484Min Clock-To-Out (ns): 6.148Max Clock-To-Out (ns): 67.071Input to OutputMin Delay (ns): 4.038Max Delay (ns): 62.340====================================================================================Compile report:===============CORE Used: 5174Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4466 | 4466SEQ | 708 | 708====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 62.489Frequency (MHz): 16.003Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 59.682External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 71.122Input to OutputMin Delay (ns): 0.000Max Delay (ns): 68.508====================================================================================Compile report:===============CORE Used: 5263Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4554 | 4554SEQ | 709 | 709====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 52.780Frequency (MHz): 18.947Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.636External Hold (ns): 0.644Min Clock-To-Out (ns): 2.870Max Clock-To-Out (ns): 60.087Input to OutputMin Delay (ns): 1.901Max Delay (ns): 58.974====================================================================================Compile report:===============CORE Used: 5246Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4538 | 4538SEQ | 708 | 708====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 44.316Frequency (MHz): 22.565Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 42.479External Hold (ns): 0.407Min Clock-To-Out (ns): 2.509Max Clock-To-Out (ns): 49.750Input to OutputMin Delay (ns): 1.888Max Delay (ns): 47.909====================================================================================Compile report:===============CORE Used: 5210Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4503 | 4503SEQ | 707 | 707====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 64.038Frequency (MHz): 15.616Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 64.165External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 68.333Input to OutputMin Delay (ns): 0.000Max Delay (ns): 69.112====================================================================================Compile report:===============CORE Used: 5263Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4554 | 4554SEQ | 709 | 709====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 56.151Frequency (MHz): 17.809Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 54.045External Hold (ns): 0.671Min Clock-To-Out (ns): 2.988Max Clock-To-Out (ns): 65.864Input to OutputMin Delay (ns): 2.209Max Delay (ns): 63.758====================================================================================Compile report:===============CORE Used: 5246Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4538 | 4538SEQ | 708 | 708====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 46.560Frequency (MHz): 21.478Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 48.940External Hold (ns): 0.720Min Clock-To-Out (ns): 2.906Max Clock-To-Out (ns): 56.528Input to OutputMin Delay (ns): 2.260Max Delay (ns): 58.908====================================================================================Compile report:===============CORE Used: 5210Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4503 | 4503SEQ | 707 | 707====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 70.004Frequency (MHz): 14.285Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 67.782External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 76.206Input to OutputMin Delay (ns): 0.000Max Delay (ns): 73.984====================================================================================Compile report:===============CORE Used: 5214Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4505 | 4505SEQ | 709 | 709====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 67.175Frequency (MHz): 14.886Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 66.999External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 74.967Input to OutputMin Delay (ns): 0.000Max Delay (ns): 74.791====================================================================================Compile report:===============CORE Used: 5571Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4821 | 4821SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 52.406Frequency (MHz): 19.082Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 49.356External Hold (ns): 0.399Min Clock-To-Out (ns): 3.024Max Clock-To-Out (ns): 58.778Input to OutputMin Delay (ns): 2.043Max Delay (ns): 57.661====================================================================================Compile report:===============CORE Used: 5345Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4595 | 4595SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 43.762Frequency (MHz): 22.851Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 42.914External Hold (ns): 0.453Min Clock-To-Out (ns): 2.938Max Clock-To-Out (ns): 52.039Input to OutputMin Delay (ns): 2.117Max Delay (ns): 50.921====================================================================================Compile report:===============CORE Used: 5446Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4696 | 4696SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 70.659Frequency (MHz): 14.152Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 69.361External Hold (ns): 1.104Min Clock-To-Out (ns): 6.284Max Clock-To-Out (ns): 79.935Input to OutputMin Delay (ns): 4.970Max Delay (ns): 78.637====================================================================================Compile report:===============CORE Used: 5453Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4703 | 4703SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 56.521Frequency (MHz): 17.693Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 53.598External Hold (ns): 0.935Min Clock-To-Out (ns): 5.720Max Clock-To-Out (ns): 64.497Input to OutputMin Delay (ns): 4.213Max Delay (ns): 61.316====================================================================================Compile report:===============CORE Used: 5418Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4668 | 4668SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 68.371Frequency (MHz): 14.626Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.231External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 75.295Input to OutputMin Delay (ns): 0.000Max Delay (ns): 72.138====================================================================================Compile report:===============CORE Used: 5571Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4821 | 4821SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 58.370Frequency (MHz): 17.132Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.910External Hold (ns): 0.260Min Clock-To-Out (ns): 2.311Max Clock-To-Out (ns): 60.896Input to OutputMin Delay (ns): 1.902Max Delay (ns): 59.108====================================================================================Compile report:===============CORE Used: 5345Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4595 | 4595SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 42.983Frequency (MHz): 23.265Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 41.687External Hold (ns): 0.668Min Clock-To-Out (ns): 2.665Max Clock-To-Out (ns): 50.200Input to OutputMin Delay (ns): 1.890Max Delay (ns): 48.904====================================================================================Compile report:===============CORE Used: 5446Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4696 | 4696SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 65.791Frequency (MHz): 15.200Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.369External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 77.776Input to OutputMin Delay (ns): 0.000Max Delay (ns): 77.354====================================================================================Compile report:===============CORE Used: 5571Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4821 | 4821SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 53.504Frequency (MHz): 18.690Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 51.043External Hold (ns): 1.020Min Clock-To-Out (ns): 2.932Max Clock-To-Out (ns): 63.905Input to OutputMin Delay (ns): 2.211Max Delay (ns): 61.444====================================================================================Compile report:===============CORE Used: 5345Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4595 | 4595SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 46.762Frequency (MHz): 21.385Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 45.886External Hold (ns): 1.039Min Clock-To-Out (ns): 2.882Max Clock-To-Out (ns): 54.605Input to OutputMin Delay (ns): 2.258Max Delay (ns): 53.727====================================================================================Compile report:===============CORE Used: 5446Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4696 | 4696SEQ | 750 | 750====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock Domain: dco_clkPeriod (ns): 69.277Frequency (MHz): 14.435Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.839External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 77.535Input to OutputMin Delay (ns): 0.000Max Delay (ns): 73.236====================================================================================Compile report:===============CORE Used: 5467Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4716 | 4716SEQ | 751 | 751====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 65.626Frequency (MHz): 15.238Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 62.017External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 71.036Input to OutputMin Delay (ns): 0.000Max Delay (ns): 68.666====================================================================================Compile report:===============CORE Used: 5747Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4954 | 4954SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 54.672Frequency (MHz): 18.291Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 49.764External Hold (ns): 0.328Min Clock-To-Out (ns): 3.161Max Clock-To-Out (ns): 61.785Input to OutputMin Delay (ns): 2.070Max Delay (ns): 56.877====================================================================================Compile report:===============CORE Used: 5713Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4920 | 4920SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3E (A3PE1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 51.406Frequency (MHz): 19.453Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 47.497External Hold (ns): 0.320Min Clock-To-Out (ns): 3.089Max Clock-To-Out (ns): 52.123Input to OutputMin Delay (ns): 2.089Max Delay (ns): 51.309====================================================================================Compile report:===============CORE Used: 5625Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4833 | 4833SEQ | 792 | 792====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 71.166Frequency (MHz): 14.052Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 65.631External Hold (ns): 1.104Min Clock-To-Out (ns): 5.982Max Clock-To-Out (ns): 81.369Input to OutputMin Delay (ns): 4.759Max Delay (ns): 75.834====================================================================================Compile report:===============CORE Used: 5638Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4846 | 4846SEQ | 792 | 792====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3L (A3P1000L), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 61.462Frequency (MHz): 16.270Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 55.362External Hold (ns): 0.356Min Clock-To-Out (ns): 5.381Max Clock-To-Out (ns): 64.619Input to OutputMin Delay (ns): 4.213Max Delay (ns): 62.829====================================================================================Compile report:===============CORE Used: 5706Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4913 | 4913SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 65.017Frequency (MHz): 15.381Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 61.568External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 70.734Input to OutputMin Delay (ns): 0.000Max Delay (ns): 67.285====================================================================================Compile report:===============CORE Used: 5747Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4954 | 4954SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 53.783Frequency (MHz): 18.593Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 50.882External Hold (ns): 0.475Min Clock-To-Out (ns): 2.731Max Clock-To-Out (ns): 59.354Input to OutputMin Delay (ns): 1.901Max Delay (ns): 56.114====================================================================================Compile report:===============CORE Used: 5713Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4920 | 4920SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# ProASIC3 (A3P1000), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 48.202Frequency (MHz): 20.746Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 45.292External Hold (ns): 0.414Min Clock-To-Out (ns): 2.463Max Clock-To-Out (ns): 53.635Input to OutputMin Delay (ns): 1.941Max Delay (ns): 51.955====================================================================================Compile report:===============CORE Used: 5625Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4833 | 4833SEQ | 792 | 792====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 64.510Frequency (MHz): 15.501Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 61.904External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 75.008Input to OutputMin Delay (ns): 0.000Max Delay (ns): 73.237====================================================================================Compile report:===============CORE Used: 5747Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4954 | 4954SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 55.618Frequency (MHz): 17.980Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 49.363External Hold (ns): 1.007Min Clock-To-Out (ns): 3.473Max Clock-To-Out (ns): 63.477Input to OutputMin Delay (ns): 2.212Max Delay (ns): 59.116====================================================================================Compile report:===============CORE Used: 5713Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4920 | 4920SEQ | 793 | 793====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# Fusion (AFS1500), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 48.568Frequency (MHz): 20.590Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 45.081External Hold (ns): 1.026Min Clock-To-Out (ns): 2.608Max Clock-To-Out (ns): 55.077Input to OutputMin Delay (ns): 2.258Max Delay (ns): 51.590====================================================================================Compile report:===============CORE Used: 5625Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4833 | 4833SEQ | 792 | 792====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS#====================================================================================# IGLOOE (AGLE600V5), speedgrade: Std#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock Domain: dco_clkPeriod (ns): 70.914Frequency (MHz): 14.102Required Period (ns): 40.000Required Frequency (MHz): 25.000External Setup (ns): 67.728External Hold (ns): 0.000Min Clock-To-Out (ns): 0.000Max Clock-To-Out (ns): 80.521Input to OutputMin Delay (ns): 0.000Max Delay (ns): 77.335====================================================================================Compile report:===============CORE Used: 5739Core Information:Type | Instances | Core tiles--------|--------------|-----------COMB | 4948 | 4948SEQ | 791 | 791====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### ANALYSIS DONE#####################################################################################
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