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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.log] - Rev 67

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#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                59.496
Frequency (MHz):            16.808
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        56.596
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      65.840

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             62.940


====================================================================================
Compile report:
===============

    CORE                     Used:   3585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3106         | 3106
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.520
Frequency (MHz):            18.012
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.193
External Hold (ns):         0.486
Min Clock-To-Out (ns):      3.058
Max Clock-To-Out (ns):      64.779

                            Input to Output
Min Delay (ns):             2.046
Max Delay (ns):             60.452


====================================================================================
Compile report:
===============

    CORE                     Used:   3635  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3156         | 3156
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                44.550
Frequency (MHz):            22.447
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        41.682
External Hold (ns):         0.248
Min Clock-To-Out (ns):      3.318
Max Clock-To-Out (ns):      51.566

                            Input to Output
Min Delay (ns):             2.088
Max Delay (ns):             48.698


====================================================================================
Compile report:
===============

    CORE                     Used:   3556  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3077         | 3077
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                69.886
Frequency (MHz):            14.309
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.083
External Hold (ns):         0.765
Min Clock-To-Out (ns):      7.615
Max Clock-To-Out (ns):      75.891

                            Input to Output
Min Delay (ns):             4.971
Max Delay (ns):             71.088


====================================================================================
Compile report:
===============

    CORE                     Used:   3549  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3069         | 3069
    SEQ     | 480          | 480


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.165
Frequency (MHz):            18.127
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.175
External Hold (ns):         0.935
Min Clock-To-Out (ns):      6.100
Max Clock-To-Out (ns):      62.347

                            Input to Output
Min Delay (ns):             4.213
Max Delay (ns):             58.357


====================================================================================
Compile report:
===============

    CORE                     Used:   3535  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3056         | 3056
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                60.713
Frequency (MHz):            16.471
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        58.080
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      67.811

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             65.178


====================================================================================
Compile report:
===============

    CORE                     Used:   3585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3106         | 3106
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.458
Frequency (MHz):            18.032
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        50.559
External Hold (ns):         0.424
Min Clock-To-Out (ns):      2.941
Max Clock-To-Out (ns):      64.709

                            Input to Output
Min Delay (ns):             1.904
Max Delay (ns):             59.812


====================================================================================
Compile report:
===============

    CORE                     Used:   3635  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3156         | 3156
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                43.859
Frequency (MHz):            22.800
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        41.325
External Hold (ns):         0.349
Min Clock-To-Out (ns):      3.018
Max Clock-To-Out (ns):      48.521

                            Input to Output
Min Delay (ns):             1.893
Max Delay (ns):             45.987


====================================================================================
Compile report:
===============

    CORE                     Used:   3556  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3077         | 3077
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                60.059
Frequency (MHz):            16.650
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        57.164
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      68.807

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             65.912


====================================================================================
Compile report:
===============

    CORE                     Used:   3585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3106         | 3106
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.859
Frequency (MHz):            17.902
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.060
External Hold (ns):         0.991
Min Clock-To-Out (ns):      3.083
Max Clock-To-Out (ns):      62.333

                            Input to Output
Min Delay (ns):             2.212
Max Delay (ns):             55.534


====================================================================================
Compile report:
===============

    CORE                     Used:   3635  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3156         | 3156
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                44.843
Frequency (MHz):            22.300
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        40.185
External Hold (ns):         1.018
Min Clock-To-Out (ns):      2.963
Max Clock-To-Out (ns):      51.927

                            Input to Output
Min Delay (ns):             2.260
Max Delay (ns):             47.269


====================================================================================
Compile report:
===============

    CORE                     Used:   3556  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3077         | 3077
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          0         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                71.404
Frequency (MHz):            14.005
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.180
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      79.196

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             72.972


====================================================================================
Compile report:
===============

    CORE                     Used:   3646  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 3167         | 3167
    SEQ     | 479          | 479


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                71.522
Frequency (MHz):            13.982
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        62.333
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      71.649

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             70.065


====================================================================================
Compile report:
===============

    CORE                     Used:   4884  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4261         | 4261
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.799
Frequency (MHz):            17.921
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        55.847
External Hold (ns):         0.430
Min Clock-To-Out (ns):      3.127
Max Clock-To-Out (ns):      62.868

                            Input to Output
Min Delay (ns):             2.070
Max Delay (ns):             62.916


====================================================================================
Compile report:
===============

    CORE                     Used:   4742  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4118         | 4118
    SEQ     | 624          | 624


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                46.678
Frequency (MHz):            21.423
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        45.726
External Hold (ns):         0.184
Min Clock-To-Out (ns):      3.121
Max Clock-To-Out (ns):      52.569

                            Input to Output
Min Delay (ns):             2.125
Max Delay (ns):             51.617


====================================================================================
Compile report:
===============

    CORE                     Used:   4811  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4188         | 4188
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                66.074
Frequency (MHz):            15.135
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.604
External Hold (ns):         0.636
Min Clock-To-Out (ns):      6.321
Max Clock-To-Out (ns):      74.907

                            Input to Output
Min Delay (ns):             4.750
Max Delay (ns):             75.465


====================================================================================
Compile report:
===============

    CORE                     Used:   4774  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4151         | 4151
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                62.880
Frequency (MHz):            15.903
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        58.918
External Hold (ns):         0.501
Min Clock-To-Out (ns):      5.767
Max Clock-To-Out (ns):      68.704

                            Input to Output
Min Delay (ns):             4.032
Max Delay (ns):             66.092


====================================================================================
Compile report:
===============

    CORE                     Used:   4776  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4153         | 4153
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                66.554
Frequency (MHz):            15.025
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        61.743
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      72.194

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             70.797


====================================================================================
Compile report:
===============

    CORE                     Used:   4884  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4261         | 4261
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                54.375
Frequency (MHz):            18.391
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        54.649
External Hold (ns):         0.420
Min Clock-To-Out (ns):      2.827
Max Clock-To-Out (ns):      59.461

                            Input to Output
Min Delay (ns):             1.902
Max Delay (ns):             59.735


====================================================================================
Compile report:
===============

    CORE                     Used:   4742  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4118         | 4118
    SEQ     | 624          | 624


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                46.154
Frequency (MHz):            21.667
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        46.484
External Hold (ns):         0.353
Min Clock-To-Out (ns):      3.003
Max Clock-To-Out (ns):      51.186

                            Input to Output
Min Delay (ns):             1.940
Max Delay (ns):             51.965


====================================================================================
Compile report:
===============

    CORE                     Used:   4811  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4188         | 4188
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                70.208
Frequency (MHz):            14.243
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        60.252
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      69.971

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             68.565


====================================================================================
Compile report:
===============

    CORE                     Used:   4884  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4261         | 4261
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                56.209
Frequency (MHz):            17.791
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        54.735
External Hold (ns):         0.685
Min Clock-To-Out (ns):      2.951
Max Clock-To-Out (ns):      61.627

                            Input to Output
Min Delay (ns):             2.212
Max Delay (ns):             60.153


====================================================================================
Compile report:
===============

    CORE                     Used:   4742  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4118         | 4118
    SEQ     | 624          | 624


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                48.594
Frequency (MHz):            20.579
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.120
External Hold (ns):         1.041
Min Clock-To-Out (ns):      2.988
Max Clock-To-Out (ns):      53.864

                            Input to Output
Min Delay (ns):             2.262
Max Delay (ns):             54.390


====================================================================================
Compile report:
===============

    CORE                     Used:   4811  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4188         | 4188
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         0            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                73.462
Frequency (MHz):            13.612
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        64.585
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      73.620

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             70.771


====================================================================================
Compile report:
===============

    CORE                     Used:   4857  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4234         | 4234
    SEQ     | 623          | 623


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                61.636
Frequency (MHz):            16.224
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        57.137
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      67.618

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             63.463


====================================================================================
Compile report:
===============

    CORE                     Used:   5014  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4348         | 4348
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                62.374
Frequency (MHz):            16.032
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        52.661
External Hold (ns):         0.369
Min Clock-To-Out (ns):      3.057
Max Clock-To-Out (ns):      60.319

                            Input to Output
Min Delay (ns):             2.079
Max Delay (ns):             57.466


====================================================================================
Compile report:
===============

    CORE                     Used:   5004  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4337         | 4337
    SEQ     | 667          | 667


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                47.073
Frequency (MHz):            21.244
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        46.714
External Hold (ns):         0.437
Min Clock-To-Out (ns):      3.315
Max Clock-To-Out (ns):      52.799

                            Input to Output
Min Delay (ns):             2.109
Max Delay (ns):             52.440


====================================================================================
Compile report:
===============

    CORE                     Used:   5002  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4336         | 4336
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                69.350
Frequency (MHz):            14.420
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        66.678
External Hold (ns):         1.139
Min Clock-To-Out (ns):      6.759
Max Clock-To-Out (ns):      73.782

                            Input to Output
Min Delay (ns):             4.757
Max Delay (ns):             72.203


====================================================================================
Compile report:
===============

    CORE                     Used:   5012  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4345         | 4345
    SEQ     | 667          | 667


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                54.514
Frequency (MHz):            18.344
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        52.044
External Hold (ns):         0.934
Min Clock-To-Out (ns):      5.679
Max Clock-To-Out (ns):      62.000

                            Input to Output
Min Delay (ns):             4.032
Max Delay (ns):             58.639


====================================================================================
Compile report:
===============

    CORE                     Used:   5032  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4366         | 4366
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                60.421
Frequency (MHz):            16.551
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        58.594
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      69.078

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             67.251


====================================================================================
Compile report:
===============

    CORE                     Used:   5014  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4348         | 4348
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                54.338
Frequency (MHz):            18.403
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.572
External Hold (ns):         0.643
Min Clock-To-Out (ns):      2.515
Max Clock-To-Out (ns):      58.728

                            Input to Output
Min Delay (ns):             1.854
Max Delay (ns):             55.962


====================================================================================
Compile report:
===============

    CORE                     Used:   5004  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4337         | 4337
    SEQ     | 667          | 667


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                47.071
Frequency (MHz):            21.245
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        47.553
External Hold (ns):         0.528
Min Clock-To-Out (ns):      2.730
Max Clock-To-Out (ns):      50.373

                            Input to Output
Min Delay (ns):             1.940
Max Delay (ns):             50.855


====================================================================================
Compile report:
===============

    CORE                     Used:   5002  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4336         | 4336
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                64.110
Frequency (MHz):            15.598
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        62.268
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      75.575

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             73.733


====================================================================================
Compile report:
===============

    CORE                     Used:   5014  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4348         | 4348
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.995
Frequency (MHz):            17.859
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        53.992
External Hold (ns):         0.998
Min Clock-To-Out (ns):      2.999
Max Clock-To-Out (ns):      62.056

                            Input to Output
Min Delay (ns):             2.211
Max Delay (ns):             60.053


====================================================================================
Compile report:
===============

    CORE                     Used:   5004  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4337         | 4337
    SEQ     | 667          | 667


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                49.346
Frequency (MHz):            20.265
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        46.472
External Hold (ns):         1.023
Min Clock-To-Out (ns):      2.997
Max Clock-To-Out (ns):      52.969

                            Input to Output
Min Delay (ns):             2.297
Max Delay (ns):             53.522


====================================================================================
Compile report:
===============

    CORE                     Used:   5002  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4336         | 4336
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            0          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                72.222
Frequency (MHz):            13.846
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        66.967
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      79.167

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             73.912


====================================================================================
Compile report:
===============

    CORE                     Used:   5016  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4350         | 4350
    SEQ     | 666          | 666


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                60.040
Frequency (MHz):            16.656
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        56.383
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      67.070

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             63.561


====================================================================================
Compile report:
===============

    CORE                     Used:   5263  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4554         | 4554
    SEQ     | 709          | 709


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                52.542
Frequency (MHz):            19.032
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.724
External Hold (ns):         0.390
Min Clock-To-Out (ns):      3.241
Max Clock-To-Out (ns):      60.476

                            Input to Output
Min Delay (ns):             2.048
Max Delay (ns):             59.658


====================================================================================
Compile report:
===============

    CORE                     Used:   5246  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4538         | 4538
    SEQ     | 708          | 708


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                41.647
Frequency (MHz):            24.011
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        40.940
External Hold (ns):         0.393
Min Clock-To-Out (ns):      3.373
Max Clock-To-Out (ns):      49.023

                            Input to Output
Min Delay (ns):             2.162
Max Delay (ns):             48.316


====================================================================================
Compile report:
===============

    CORE                     Used:   5210  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4503         | 4503
    SEQ     | 707          | 707


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                67.866
Frequency (MHz):            14.735
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        67.341
External Hold (ns):         0.633
Min Clock-To-Out (ns):      6.638
Max Clock-To-Out (ns):      77.183

                            Input to Output
Min Delay (ns):             4.759
Max Delay (ns):             76.658


====================================================================================
Compile report:
===============

    CORE                     Used:   5183  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4474         | 4474
    SEQ     | 709          | 709


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                58.347
Frequency (MHz):            17.139
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        53.616
External Hold (ns):         0.484
Min Clock-To-Out (ns):      6.148
Max Clock-To-Out (ns):      67.071

                            Input to Output
Min Delay (ns):             4.038
Max Delay (ns):             62.340


====================================================================================
Compile report:
===============

    CORE                     Used:   5174  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4466         | 4466
    SEQ     | 708          | 708


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                62.489
Frequency (MHz):            16.003
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        59.682
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      71.122

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             68.508


====================================================================================
Compile report:
===============

    CORE                     Used:   5263  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4554         | 4554
    SEQ     | 709          | 709


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                52.780
Frequency (MHz):            18.947
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.636
External Hold (ns):         0.644
Min Clock-To-Out (ns):      2.870
Max Clock-To-Out (ns):      60.087

                            Input to Output
Min Delay (ns):             1.901
Max Delay (ns):             58.974


====================================================================================
Compile report:
===============

    CORE                     Used:   5246  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4538         | 4538
    SEQ     | 708          | 708


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                44.316
Frequency (MHz):            22.565
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        42.479
External Hold (ns):         0.407
Min Clock-To-Out (ns):      2.509
Max Clock-To-Out (ns):      49.750

                            Input to Output
Min Delay (ns):             1.888
Max Delay (ns):             47.909


====================================================================================
Compile report:
===============

    CORE                     Used:   5210  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4503         | 4503
    SEQ     | 707          | 707


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                64.038
Frequency (MHz):            15.616
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        64.165
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      68.333

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             69.112


====================================================================================
Compile report:
===============

    CORE                     Used:   5263  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4554         | 4554
    SEQ     | 709          | 709


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                56.151
Frequency (MHz):            17.809
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        54.045
External Hold (ns):         0.671
Min Clock-To-Out (ns):      2.988
Max Clock-To-Out (ns):      65.864

                            Input to Output
Min Delay (ns):             2.209
Max Delay (ns):             63.758


====================================================================================
Compile report:
===============

    CORE                     Used:   5246  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4538         | 4538
    SEQ     | 708          | 708


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                46.560
Frequency (MHz):            21.478
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        48.940
External Hold (ns):         0.720
Min Clock-To-Out (ns):      2.906
Max Clock-To-Out (ns):      56.528

                            Input to Output
Min Delay (ns):             2.260
Max Delay (ns):             58.908


====================================================================================
Compile report:
===============

    CORE                     Used:   5210  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4503         | 4503
    SEQ     | 707          | 707


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          0            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                70.004
Frequency (MHz):            14.285
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        67.782
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      76.206

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             73.984


====================================================================================
Compile report:
===============

    CORE                     Used:   5214  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4505         | 4505
    SEQ     | 709          | 709


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                67.175
Frequency (MHz):            14.886
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        66.999
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      74.967

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             74.791


====================================================================================
Compile report:
===============

    CORE                     Used:   5571  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4821         | 4821
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                52.406
Frequency (MHz):            19.082
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.356
External Hold (ns):         0.399
Min Clock-To-Out (ns):      3.024
Max Clock-To-Out (ns):      58.778

                            Input to Output
Min Delay (ns):             2.043
Max Delay (ns):             57.661


====================================================================================
Compile report:
===============

    CORE                     Used:   5345  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4595         | 4595
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                43.762
Frequency (MHz):            22.851
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        42.914
External Hold (ns):         0.453
Min Clock-To-Out (ns):      2.938
Max Clock-To-Out (ns):      52.039

                            Input to Output
Min Delay (ns):             2.117
Max Delay (ns):             50.921


====================================================================================
Compile report:
===============

    CORE                     Used:   5446  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4696         | 4696
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                70.659
Frequency (MHz):            14.152
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        69.361
External Hold (ns):         1.104
Min Clock-To-Out (ns):      6.284
Max Clock-To-Out (ns):      79.935

                            Input to Output
Min Delay (ns):             4.970
Max Delay (ns):             78.637


====================================================================================
Compile report:
===============

    CORE                     Used:   5453  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4703         | 4703
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                56.521
Frequency (MHz):            17.693
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        53.598
External Hold (ns):         0.935
Min Clock-To-Out (ns):      5.720
Max Clock-To-Out (ns):      64.497

                            Input to Output
Min Delay (ns):             4.213
Max Delay (ns):             61.316


====================================================================================
Compile report:
===============

    CORE                     Used:   5418  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4668         | 4668
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                68.371
Frequency (MHz):            14.626
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.231
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      75.295

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             72.138


====================================================================================
Compile report:
===============

    CORE                     Used:   5571  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4821         | 4821
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                58.370
Frequency (MHz):            17.132
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.910
External Hold (ns):         0.260
Min Clock-To-Out (ns):      2.311
Max Clock-To-Out (ns):      60.896

                            Input to Output
Min Delay (ns):             1.902
Max Delay (ns):             59.108


====================================================================================
Compile report:
===============

    CORE                     Used:   5345  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4595         | 4595
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                42.983
Frequency (MHz):            23.265
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        41.687
External Hold (ns):         0.668
Min Clock-To-Out (ns):      2.665
Max Clock-To-Out (ns):      50.200

                            Input to Output
Min Delay (ns):             1.890
Max Delay (ns):             48.904


====================================================================================
Compile report:
===============

    CORE                     Used:   5446  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4696         | 4696
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                65.791
Frequency (MHz):            15.200
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.369
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      77.776

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             77.354


====================================================================================
Compile report:
===============

    CORE                     Used:   5571  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4821         | 4821
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                53.504
Frequency (MHz):            18.690
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        51.043
External Hold (ns):         1.020
Min Clock-To-Out (ns):      2.932
Max Clock-To-Out (ns):      63.905

                            Input to Output
Min Delay (ns):             2.211
Max Delay (ns):             61.444


====================================================================================
Compile report:
===============

    CORE                     Used:   5345  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4595         | 4595
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                46.762
Frequency (MHz):            21.385
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        45.886
External Hold (ns):         1.039
Min Clock-To-Out (ns):      2.882
Max Clock-To-Out (ns):      54.605

                            Input to Output
Min Delay (ns):             2.258
Max Delay (ns):             53.727


====================================================================================
Compile report:
===============

    CORE                     Used:   5446  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4696         | 4696
    SEQ     | 750          | 750


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            0    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                69.277
Frequency (MHz):            14.435
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.839
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      77.535

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             73.236


====================================================================================
Compile report:
===============

    CORE                     Used:   5467  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4716         | 4716
    SEQ     | 751          | 751


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                65.626
Frequency (MHz):            15.238
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        62.017
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      71.036

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             68.666


====================================================================================
Compile report:
===============

    CORE                     Used:   5747  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4954         | 4954
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                54.672
Frequency (MHz):            18.291
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.764
External Hold (ns):         0.328
Min Clock-To-Out (ns):      3.161
Max Clock-To-Out (ns):      61.785

                            Input to Output
Min Delay (ns):             2.070
Max Delay (ns):             56.877


====================================================================================
Compile report:
===============

    CORE                     Used:   5713  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4920         | 4920
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                51.406
Frequency (MHz):            19.453
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        47.497
External Hold (ns):         0.320
Min Clock-To-Out (ns):      3.089
Max Clock-To-Out (ns):      52.123

                            Input to Output
Min Delay (ns):             2.089
Max Delay (ns):             51.309


====================================================================================
Compile report:
===============

    CORE                     Used:   5625  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4833         | 4833
    SEQ     | 792          | 792


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                71.166
Frequency (MHz):            14.052
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        65.631
External Hold (ns):         1.104
Min Clock-To-Out (ns):      5.982
Max Clock-To-Out (ns):      81.369

                            Input to Output
Min Delay (ns):             4.759
Max Delay (ns):             75.834


====================================================================================
Compile report:
===============

    CORE                     Used:   5638  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4846         | 4846
    SEQ     | 792          | 792


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                61.462
Frequency (MHz):            16.270
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        55.362
External Hold (ns):         0.356
Min Clock-To-Out (ns):      5.381
Max Clock-To-Out (ns):      64.619

                            Input to Output
Min Delay (ns):             4.213
Max Delay (ns):             62.829


====================================================================================
Compile report:
===============

    CORE                     Used:   5706  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4913         | 4913
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                65.017
Frequency (MHz):            15.381
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        61.568
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      70.734

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             67.285


====================================================================================
Compile report:
===============

    CORE                     Used:   5747  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4954         | 4954
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                53.783
Frequency (MHz):            18.593
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        50.882
External Hold (ns):         0.475
Min Clock-To-Out (ns):      2.731
Max Clock-To-Out (ns):      59.354

                            Input to Output
Min Delay (ns):             1.901
Max Delay (ns):             56.114


====================================================================================
Compile report:
===============

    CORE                     Used:   5713  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4920         | 4920
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                48.202
Frequency (MHz):            20.746
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        45.292
External Hold (ns):         0.414
Min Clock-To-Out (ns):      2.463
Max Clock-To-Out (ns):      53.635

                            Input to Output
Min Delay (ns):             1.941
Max Delay (ns):             51.955


====================================================================================
Compile report:
===============

    CORE                     Used:   5625  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4833         | 4833
    SEQ     | 792          | 792


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                64.510
Frequency (MHz):            15.501
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        61.904
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      75.008

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             73.237


====================================================================================
Compile report:
===============

    CORE                     Used:   5747  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4954         | 4954
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                55.618
Frequency (MHz):            17.980
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.363
External Hold (ns):         1.007
Min Clock-To-Out (ns):      3.473
Max Clock-To-Out (ns):      63.477

                            Input to Output
Min Delay (ns):             2.212
Max Delay (ns):             59.116


====================================================================================
Compile report:
===============

    CORE                     Used:   5713  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4920         | 4920
    SEQ     | 793          | 793


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                48.568
Frequency (MHz):            20.590
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        45.081
External Hold (ns):         1.026
Min Clock-To-Out (ns):      2.608
Max Clock-To-Out (ns):      55.077

                            Input to Output
Min Delay (ns):             2.258
Max Delay (ns):             51.590


====================================================================================
Compile report:
===============

    CORE                     Used:   5625  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4833         | 4833
    SEQ     | 792          | 792


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
#     12          10          1         1            1          1            1    
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                70.914
Frequency (MHz):            14.102
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        67.728
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      80.521

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             77.335


====================================================================================
Compile report:
===============

    CORE                     Used:   5739  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4948         | 4948
    SEQ     | 791          | 791


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################


#####################################################################################
#                            ANALYSIS DONE
#####################################################################################

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