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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.mpy.log] - Rev 208

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#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                61.969
Frequency (MHz):            16.137
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        60.413
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      72.849

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             71.293


====================================================================================
Compile report:
===============

    CORE                     Used:   4734  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4184         | 4184
    SEQ     | 550          | 550


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                52.723
Frequency (MHz):            18.967
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.425
External Hold (ns):         0.276
Min Clock-To-Out (ns):      3.206
Max Clock-To-Out (ns):      58.337

                            Input to Output
Min Delay (ns):             2.045
Max Delay (ns):             55.039


====================================================================================
Compile report:
===============

    CORE                     Used:   4585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4033         | 4033
    SEQ     | 552          | 552


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3E (A3PE1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                47.977
Frequency (MHz):            20.843
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        44.738
External Hold (ns):         0.216
Min Clock-To-Out (ns):      3.281
Max Clock-To-Out (ns):      52.477

                            Input to Output
Min Delay (ns):             2.088
Max Delay (ns):             49.238


====================================================================================
Compile report:
===============

    CORE                     Used:   4573  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4020         | 4020
    SEQ     | 553          | 553


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                70.092
Frequency (MHz):            14.267
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        67.167
External Hold (ns):         0.206
Min Clock-To-Out (ns):      7.443
Max Clock-To-Out (ns):      78.104

                            Input to Output
Min Delay (ns):             4.745
Max Delay (ns):             75.179


====================================================================================
Compile report:
===============

    CORE                     Used:   4665  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4113         | 4113
    SEQ     | 552          | 552


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3L (A3P1000L), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                57.781
Frequency (MHz):            17.307
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        56.549
External Hold (ns):         0.295
Min Clock-To-Out (ns):      6.027
Max Clock-To-Out (ns):      65.937

                            Input to Output
Min Delay (ns):             4.220
Max Delay (ns):             64.705


====================================================================================
Compile report:
===============

    CORE                     Used:   4595  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4044         | 4044
    SEQ     | 551          | 551


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                64.007
Frequency (MHz):            15.623
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        62.387
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      71.427

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             69.807


====================================================================================
Compile report:
===============

    CORE                     Used:   4734  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4184         | 4184
    SEQ     | 550          | 550


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                52.047
Frequency (MHz):            19.213
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        49.153
External Hold (ns):         0.379
Min Clock-To-Out (ns):      3.098
Max Clock-To-Out (ns):      59.549

                            Input to Output
Min Delay (ns):             1.854
Max Delay (ns):             56.655


====================================================================================
Compile report:
===============

    CORE                     Used:   4585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4033         | 4033
    SEQ     | 552          | 552


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# ProASIC3 (A3P1000), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                45.521
Frequency (MHz):            21.968
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        42.871
External Hold (ns):         0.659
Min Clock-To-Out (ns):      3.201
Max Clock-To-Out (ns):      50.665

                            Input to Output
Min Delay (ns):             1.940
Max Delay (ns):             48.015


====================================================================================
Compile report:
===============

    CORE                     Used:   4573  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4020         | 4020
    SEQ     | 553          | 553


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                63.147
Frequency (MHz):            15.836
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        59.732
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      73.607

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             70.192


====================================================================================
Compile report:
===============

    CORE                     Used:   4734  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4184         | 4184
    SEQ     | 550          | 550


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -1
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                54.158
Frequency (MHz):            18.464
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        46.454
External Hold (ns):         0.600
Min Clock-To-Out (ns):      3.076
Max Clock-To-Out (ns):      62.871

                            Input to Output
Min Delay (ns):             2.213
Max Delay (ns):             55.167


====================================================================================
Compile report:
===============

    CORE                     Used:   4585  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4033         | 4033
    SEQ     | 552          | 552


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# Fusion (AFS1500), speedgrade: -2
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                46.868
Frequency (MHz):            21.337
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        41.526
External Hold (ns):         0.613
Min Clock-To-Out (ns):      3.009
Max Clock-To-Out (ns):      52.492

                            Input to Output
Min Delay (ns):             2.258
Max Delay (ns):             47.150


====================================================================================
Compile report:
===============

    CORE                     Used:   4573  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4020         | 4020
    SEQ     | 553          | 553


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################

#####################################################################################
#                            START SYNTHESIS
#====================================================================================
# IGLOOE (AGLE600V5), speedgrade: Std
#====================================================================================
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
#     12          10          0         0            0          0            0         1
#====================================================================================


Clock Domain:               dco_clk
Period (ns):                68.930
Frequency (MHz):            14.507
Required Period (ns):       40.000
Required Frequency (MHz):   25.000
External Setup (ns):        66.686
External Hold (ns):         0.000
Min Clock-To-Out (ns):      0.000
Max Clock-To-Out (ns):      76.255

                            Input to Output
Min Delay (ns):             0.000
Max Delay (ns):             74.011


====================================================================================
Compile report:
===============

    CORE                     Used:   4844  
Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 4292         | 4292
    SEQ     | 552          | 552


====================================================================================
#                            SYNTHESIS DONE
#####################################################################################


#####################################################################################
#                            ANALYSIS DONE
#####################################################################################

Go to most recent revision | Compare with Previous | Blame | View Log

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