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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [openMSP430_fpga.ucf] - Rev 110
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#=============================================================================
# Copyright (C) 2001 Authors
#
# This source file may be used and distributed without restriction provided
# that this copyright statement is not removed from the file and that any
# derivative work contains the original copyright notice and the associated
# disclaimer.
#
# This source file is free software; you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published
# by the Free Software Foundation; either version 2.1 of the License, or
# (at your option) any later version.
#
# This source is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
# License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this source; if not, write to the Free Software Foundation,
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#-----------------------------------------------------------------------------
#
# File Name: openMSP430_fpga.ucf
#
# Author(s):
# - Olivier Girard, olgirard@gmail.com
#
#-----------------------------------------------------------------------------
# $Rev: 26 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2009-12-19 13:25:10 +0100 (Sat, 19 Dec 2009) $
#=============================================================================
#-----------------------------------------------------------------------------#
# Clock configuration & ROM Block Assignments #
#-----------------------------------------------------------------------------#
# CLOCKS Definition
<COMMENT>NET "dco_clk" PERIOD = <PERIOD> nS LOW <HALF_PERIOD> nS;
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