URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.area.log] - Rev 141
Go to most recent revision | Compare with Previous | Blame | View Log
###################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.257| | | 1.564|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 898 out of 3584 25%Number of Slice Flip Flops: 458 out of 7168 6%Number of 4 input LUTs: 1609 out of 7168 22%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%IOB Flip Flops: 14Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.419| | | 1.361|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 898 out of 3584 25%Number of Slice Flip Flops: 458 out of 7168 6%Number of 4 input LUTs: 1609 out of 7168 22%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%IOB Flip Flops: 14Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.815| | | 1.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 903 out of 4656 19%Number of Slice Flip Flops: 458 out of 9312 4%Number of 4 input LUTs: 1615 out of 9312 17%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%IOB Flip Flops: 14Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.547| | | 1.276|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 903 out of 4656 19%Number of Slice Flip Flops: 458 out of 9312 4%Number of 4 input LUTs: 1615 out of 9312 17%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%IOB Flip Flops: 14Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.308| | | 1.511|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 911 out of 5888 15%Number of Slice Flip Flops: 459 out of 11776 3%Number of 4 input LUTs: 1629 out of 11776 13%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%IOB Flip Flops: 14Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 34.264| | | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 908 out of 5888 15%Number of Slice Flip Flops: 459 out of 11776 3%Number of 4 input LUTs: 1622 out of 11776 13%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%IOB Flip Flops: 14Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.189| | | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 913 out of 16640 5%Number of Slice Flip Flops: 459 out of 33280 1%Number of 4 input LUTs: 1628 out of 33280 4%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%IOB Flip Flops: 14Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.333| | | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 911 out of 16640 5%Number of Slice Flip Flops: 459 out of 33280 1%Number of 4 input LUTs: 1621 out of 33280 4%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%IOB Flip Flops: 14Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.902| 5.802| 2.842| 2.681|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 459 out of 54576 0%Number of Slice LUTs: 1277 out of 27288 4%Number used as Logic: 1277 out of 27288 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1303Number with an unused Flip Flop: 844 out of 1303 64%Number with an unused LUT: 26 out of 1303 1%Number of fully used LUT-FF pairs: 433 out of 1303 33%Number of unique control sets: 45IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.567| 4.891| 2.052| 1.687|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 459 out of 54576 0%Number of Slice LUTs: 1271 out of 27288 4%Number used as Logic: 1271 out of 27288 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1296Number with an unused Flip Flop: 837 out of 1296 64%Number with an unused LUT: 25 out of 1296 1%Number of fully used LUT-FF pairs: 434 out of 1296 33%Number of unique control sets: 45IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.735| 4.685| 1.744| 1.583|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 459 out of 54576 0%Number of Slice LUTs: 1267 out of 27288 4%Number used as Logic: 1267 out of 27288 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1292Number with an unused Flip Flop: 833 out of 1292 64%Number with an unused LUT: 25 out of 1292 1%Number of fully used LUT-FF pairs: 434 out of 1292 33%Number of unique control sets: 45IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.754| | | 1.115|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 911 out of 10752 8%Number of Slice Flip Flops: 459 out of 21504 2%Number of 4 input LUTs: 1629 out of 21504 7%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops: 14Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.719| | | 0.952|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 912 out of 10752 8%Number of Slice Flip Flops: 459 out of 21504 2%Number of 4 input LUTs: 1632 out of 21504 7%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops: 14Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.362| | | 0.846|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 910 out of 10752 8%Number of Slice Flip Flops: 459 out of 21504 2%Number of 4 input LUTs: 1627 out of 21504 7%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops: 14Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.457| | | 1.310|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 458 out of 19200 2%Number of Slice LUTs: 1219 out of 19200 6%Number used as Logic: 1219 out of 19200 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1245Number with an unused Flip Flop: 787 out of 1245 63%Number with an unused LUT: 26 out of 1245 2%Number of fully used LUT-FF pairs: 432 out of 1245 34%Number of unique control sets: 43IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.062| | | 0.682|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 458 out of 19200 2%Number of Slice LUTs: 1221 out of 19200 6%Number used as Logic: 1221 out of 19200 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1247Number with an unused Flip Flop: 789 out of 1247 63%Number with an unused LUT: 26 out of 1247 2%Number of fully used LUT-FF pairs: 432 out of 1247 34%Number of unique control sets: 43IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.982| | | 0.605|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 458 out of 19200 2%Number of Slice LUTs: 1215 out of 19200 6%Number used as Logic: 1215 out of 19200 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1241Number with an unused Flip Flop: 783 out of 1241 63%Number with an unused LUT: 26 out of 1241 2%Number of fully used LUT-FF pairs: 432 out of 1241 34%Number of unique control sets: 43IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.415| 3.960| 2.270| 0.606|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 458 out of 93120 0%Number of Slice LUTs: 1237 out of 46560 2%Number used as Logic: 1237 out of 46560 2%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1263Number with an unused Flip Flop: 805 out of 1263 63%Number with an unused LUT: 26 out of 1263 2%Number of fully used LUT-FF pairs: 432 out of 1263 34%Number of unique control sets: 44IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.658| 2.819| 1.524| 0.593|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 458 out of 93120 0%Number of Slice LUTs: 1235 out of 46560 2%Number used as Logic: 1235 out of 46560 2%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1261Number with an unused Flip Flop: 803 out of 1261 63%Number with an unused LUT: 26 out of 1261 2%Number of fully used LUT-FF pairs: 432 out of 1261 34%Number of unique control sets: 44IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.295| 3.146| 1.265| 0.463|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 458 out of 93120 0%Number of Slice LUTs: 1234 out of 46560 2%Number used as Logic: 1234 out of 46560 2%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1260Number with an unused Flip Flop: 802 out of 1260 63%Number with an unused LUT: 26 out of 1260 2%Number of fully used LUT-FF pairs: 432 out of 1260 34%Number of unique control sets: 44IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%IOB Flip Flops/Latches: 14Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.357| 24.190| | 3.304|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1190 out of 3584 33%Number of Slice Flip Flops: 594 out of 7168 8%Number of 4 input LUTs: 2125 out of 7168 29%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.462| 21.414| | 1.369|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1191 out of 3584 33%Number of Slice Flip Flops: 594 out of 7168 8%Number of 4 input LUTs: 2127 out of 7168 29%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 38.168| 23.835| | 1.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1191 out of 4656 25%Number of Slice Flip Flops: 594 out of 9312 6%Number of 4 input LUTs: 2131 out of 9312 22%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.433| 20.585| | 1.175|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1191 out of 4656 25%Number of Slice Flip Flops: 594 out of 9312 6%Number of 4 input LUTs: 2131 out of 9312 22%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.728| 25.503| | 2.123|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1197 out of 5888 20%Number of Slice Flip Flops: 595 out of 11776 5%Number of 4 input LUTs: 2139 out of 11776 18%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.772| 22.023| | 1.054|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1195 out of 5888 20%Number of Slice Flip Flops: 595 out of 11776 5%Number of 4 input LUTs: 2138 out of 11776 18%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 42.462| 23.196| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1199 out of 16640 7%Number of Slice Flip Flops: 595 out of 33280 1%Number of 4 input LUTs: 2140 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 38.048| 20.537| | 1.250|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1197 out of 16640 7%Number of Slice Flip Flops: 595 out of 33280 1%Number of 4 input LUTs: 2136 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.658| 19.315| 5.207| 2.770|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 595 out of 54576 1%Number of Slice LUTs: 1620 out of 27288 5%Number used as Logic: 1620 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1648Number with an unused Flip Flop: 1053 out of 1648 63%Number with an unused LUT: 28 out of 1648 1%Number of fully used LUT-FF pairs: 567 out of 1648 34%Number of unique control sets: 56IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.045| 14.969| 3.841| 2.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 595 out of 54576 1%Number of Slice LUTs: 1603 out of 27288 5%Number used as Logic: 1603 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1631Number with an unused Flip Flop: 1036 out of 1631 63%Number with an unused LUT: 28 out of 1631 1%Number of fully used LUT-FF pairs: 567 out of 1631 34%Number of unique control sets: 56IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.652| 11.966| 3.681| 1.737|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 595 out of 54576 1%Number of Slice LUTs: 1603 out of 27288 5%Number used as Logic: 1603 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1631Number with an unused Flip Flop: 1036 out of 1631 63%Number with an unused LUT: 28 out of 1631 1%Number of fully used LUT-FF pairs: 567 out of 1631 34%Number of unique control sets: 56IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.165| 14.340| | 1.208|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1206 out of 10752 11%Number of Slice Flip Flops: 595 out of 21504 2%Number of 4 input LUTs: 2151 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.962| 12.473| | 1.486|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1206 out of 10752 11%Number of Slice Flip Flops: 595 out of 21504 2%Number of 4 input LUTs: 2152 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.351| 10.203| | 0.914|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1206 out of 10752 11%Number of Slice Flip Flops: 595 out of 21504 2%Number of 4 input LUTs: 2152 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.907| 10.911| | 0.797|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 594 out of 19200 3%Number of Slice LUTs: 1601 out of 19200 8%Number used as Logic: 1601 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1625Number with an unused Flip Flop: 1031 out of 1625 63%Number with an unused LUT: 24 out of 1625 1%Number of fully used LUT-FF pairs: 570 out of 1625 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.682| 10.151| | 0.677|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 594 out of 19200 3%Number of Slice LUTs: 1601 out of 19200 8%Number used as Logic: 1601 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1625Number with an unused Flip Flop: 1031 out of 1625 63%Number with an unused LUT: 24 out of 1625 1%Number of fully used LUT-FF pairs: 570 out of 1625 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.485| 7.831| | 0.605|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 594 out of 19200 3%Number of Slice LUTs: 1602 out of 19200 8%Number used as Logic: 1602 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1626Number with an unused Flip Flop: 1032 out of 1626 63%Number with an unused LUT: 24 out of 1626 1%Number of fully used LUT-FF pairs: 570 out of 1626 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.710| 8.922| 2.179| 0.833|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 594 out of 93120 0%Number of Slice LUTs: 1585 out of 46560 3%Number used as Logic: 1585 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1612Number with an unused Flip Flop: 1018 out of 1612 63%Number with an unused LUT: 27 out of 1612 1%Number of fully used LUT-FF pairs: 567 out of 1612 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.667| 7.873| 2.748| 0.708|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 594 out of 93120 0%Number of Slice LUTs: 1582 out of 46560 3%Number used as Logic: 1582 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1609Number with an unused Flip Flop: 1015 out of 1609 63%Number with an unused LUT: 27 out of 1609 1%Number of fully used LUT-FF pairs: 567 out of 1609 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.845| 6.840| 1.931| 0.446|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 594 out of 93120 0%Number of Slice LUTs: 1579 out of 46560 3%Number used as Logic: 1579 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1606Number with an unused Flip Flop: 1012 out of 1606 63%Number with an unused LUT: 27 out of 1606 1%Number of fully used LUT-FF pairs: 567 out of 1606 35%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 48.336| 23.967| | 1.564|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1211 out of 3584 33%Number of Slice Flip Flops: 637 out of 7168 8%Number of 4 input LUTs: 2165 out of 7168 30%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 43.503| 21.623| | 1.361|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1211 out of 3584 33%Number of Slice Flip Flops: 637 out of 7168 8%Number of 4 input LUTs: 2166 out of 7168 30%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 49.490| 24.741| | 1.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1220 out of 4656 26%Number of Slice Flip Flops: 637 out of 9312 6%Number of 4 input LUTs: 2185 out of 9312 23%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.827| 20.673| | 1.276|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1219 out of 4656 26%Number of Slice Flip Flops: 637 out of 9312 6%Number of 4 input LUTs: 2184 out of 9312 23%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 51.124| 25.734| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1225 out of 5888 20%Number of Slice Flip Flops: 638 out of 11776 5%Number of 4 input LUTs: 2191 out of 11776 18%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.403| 20.202| | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1222 out of 5888 20%Number of Slice Flip Flops: 638 out of 11776 5%Number of 4 input LUTs: 2187 out of 11776 18%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 47.780| 24.549| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1230 out of 16640 7%Number of Slice Flip Flops: 638 out of 33280 1%Number of 4 input LUTs: 2197 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.816| 19.647| | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1229 out of 16640 7%Number of Slice Flip Flops: 638 out of 33280 1%Number of 4 input LUTs: 2196 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 38.405| 19.013| 4.808| 2.271|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 638 out of 54576 1%Number of Slice LUTs: 1705 out of 27288 6%Number used as Logic: 1705 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1748Number with an unused Flip Flop: 1110 out of 1748 63%Number with an unused LUT: 43 out of 1748 2%Number of fully used LUT-FF pairs: 595 out of 1748 34%Number of unique control sets: 59IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 28.140| 15.305| 3.191| 2.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 638 out of 54576 1%Number of Slice LUTs: 1685 out of 27288 6%Number used as Logic: 1685 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1728Number with an unused Flip Flop: 1090 out of 1728 63%Number with an unused LUT: 43 out of 1728 2%Number of fully used LUT-FF pairs: 595 out of 1728 34%Number of unique control sets: 59IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.628| 12.205| 3.755| 1.850|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 638 out of 54576 1%Number of Slice LUTs: 1681 out of 27288 6%Number used as Logic: 1681 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1724Number with an unused Flip Flop: 1086 out of 1724 62%Number with an unused LUT: 43 out of 1724 2%Number of fully used LUT-FF pairs: 595 out of 1724 34%Number of unique control sets: 59IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.882| 16.025| | 0.943|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1229 out of 10752 11%Number of Slice Flip Flops: 638 out of 21504 2%Number of 4 input LUTs: 2200 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 28.466| 14.086| | 0.793|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1230 out of 10752 11%Number of Slice Flip Flops: 638 out of 21504 2%Number of 4 input LUTs: 2202 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.889| 12.458| | 0.706|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1229 out of 10752 11%Number of Slice Flip Flops: 638 out of 21504 2%Number of 4 input LUTs: 2199 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.493| 9.719| | 1.337|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 637 out of 19200 3%Number of Slice LUTs: 1691 out of 19200 8%Number used as Logic: 1691 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1727Number with an unused Flip Flop: 1090 out of 1727 63%Number with an unused LUT: 36 out of 1727 2%Number of fully used LUT-FF pairs: 601 out of 1727 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.563| 8.229| | 0.825|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 637 out of 19200 3%Number of Slice LUTs: 1692 out of 19200 8%Number used as Logic: 1692 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1728Number with an unused Flip Flop: 1091 out of 1728 63%Number with an unused LUT: 36 out of 1728 2%Number of fully used LUT-FF pairs: 601 out of 1728 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.059| 7.517| | 0.971|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 637 out of 19200 3%Number of Slice LUTs: 1692 out of 19200 8%Number used as Logic: 1692 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1728Number with an unused Flip Flop: 1091 out of 1728 63%Number with an unused LUT: 36 out of 1728 2%Number of fully used LUT-FF pairs: 601 out of 1728 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.087| 9.148| 2.687| 0.849|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 637 out of 93120 0%Number of Slice LUTs: 1673 out of 46560 3%Number used as Logic: 1673 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1715Number with an unused Flip Flop: 1078 out of 1715 62%Number with an unused LUT: 42 out of 1715 2%Number of fully used LUT-FF pairs: 595 out of 1715 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.126| 7.696| 2.168| 0.568|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 637 out of 93120 0%Number of Slice LUTs: 1668 out of 46560 3%Number used as Logic: 1668 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1710Number with an unused Flip Flop: 1073 out of 1710 62%Number with an unused LUT: 42 out of 1710 2%Number of fully used LUT-FF pairs: 595 out of 1710 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.814| 7.705| 1.615| 0.540|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 637 out of 93120 0%Number of Slice LUTs: 1668 out of 46560 3%Number used as Logic: 1668 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1710Number with an unused Flip Flop: 1073 out of 1710 62%Number with an unused LUT: 42 out of 1710 2%Number of fully used LUT-FF pairs: 595 out of 1710 34%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 49.666| 23.480| | 1.564|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1268 out of 3584 35%Number of Slice Flip Flops: 679 out of 7168 9%Number of 4 input LUTs: 2272 out of 7168 31%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 44.646| 22.025| | 1.369|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1271 out of 3584 35%Number of Slice Flip Flops: 679 out of 7168 9%Number of 4 input LUTs: 2276 out of 7168 31%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 48.181| 24.402| | 1.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1285 out of 4656 27%Number of Slice Flip Flops: 679 out of 9312 7%Number of 4 input LUTs: 2298 out of 9312 24%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.477| 20.632| | 1.175|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1283 out of 4656 27%Number of Slice Flip Flops: 679 out of 9312 7%Number of 4 input LUTs: 2295 out of 9312 24%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 49.676| 24.544| | 1.954|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1290 out of 5888 21%Number of Slice Flip Flops: 680 out of 11776 5%Number of 4 input LUTs: 2304 out of 11776 19%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 44.364| 21.845| | 1.054|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1289 out of 5888 21%Number of Slice Flip Flops: 680 out of 11776 5%Number of 4 input LUTs: 2302 out of 11776 19%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 50.009| 24.206| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1294 out of 16640 7%Number of Slice Flip Flops: 680 out of 33280 2%Number of 4 input LUTs: 2310 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.016| 20.465| | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1295 out of 16640 7%Number of Slice Flip Flops: 680 out of 33280 2%Number of 4 input LUTs: 2312 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 38.244| 19.973| 3.594| 2.681|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 680 out of 54576 1%Number of Slice LUTs: 1774 out of 27288 6%Number used as Logic: 1774 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1831Number with an unused Flip Flop: 1151 out of 1831 62%Number with an unused LUT: 57 out of 1831 3%Number of fully used LUT-FF pairs: 623 out of 1831 34%Number of unique control sets: 62IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 28.378| 14.782| 3.376| 2.037|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 680 out of 54576 1%Number of Slice LUTs: 1753 out of 27288 6%Number used as Logic: 1753 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1810Number with an unused Flip Flop: 1130 out of 1810 62%Number with an unused LUT: 57 out of 1810 3%Number of fully used LUT-FF pairs: 623 out of 1810 34%Number of unique control sets: 62IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 26.515| 13.709| 3.445| 1.490|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 680 out of 54576 1%Number of Slice LUTs: 1750 out of 27288 6%Number used as Logic: 1750 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1807Number with an unused Flip Flop: 1127 out of 1807 62%Number with an unused LUT: 57 out of 1807 3%Number of fully used LUT-FF pairs: 623 out of 1807 34%Number of unique control sets: 62IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 35.922| 17.864| | 1.208|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1287 out of 10752 11%Number of Slice Flip Flops: 680 out of 21504 3%Number of 4 input LUTs: 2305 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.389| 14.672| | 0.807|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1288 out of 10752 11%Number of Slice Flip Flops: 680 out of 21504 3%Number of 4 input LUTs: 2307 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.991| 12.374| | 0.894|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1287 out of 10752 11%Number of Slice Flip Flops: 680 out of 21504 3%Number of 4 input LUTs: 2305 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.544| 9.824| | 1.314|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 679 out of 19200 3%Number of Slice LUTs: 1753 out of 19200 9%Number used as Logic: 1753 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1812Number with an unused Flip Flop: 1133 out of 1812 62%Number with an unused LUT: 59 out of 1812 3%Number of fully used LUT-FF pairs: 620 out of 1812 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.151| 8.401| | 0.715|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 679 out of 19200 3%Number of Slice LUTs: 1752 out of 19200 9%Number used as Logic: 1752 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1811Number with an unused Flip Flop: 1132 out of 1811 62%Number with an unused LUT: 59 out of 1811 3%Number of fully used LUT-FF pairs: 620 out of 1811 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.086| 8.135| | 0.979|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 679 out of 19200 3%Number of Slice LUTs: 1751 out of 19200 9%Number used as Logic: 1751 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1810Number with an unused Flip Flop: 1131 out of 1810 62%Number with an unused LUT: 59 out of 1810 3%Number of fully used LUT-FF pairs: 620 out of 1810 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.029| 9.072| 2.246| 0.694|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 679 out of 93120 0%Number of Slice LUTs: 1746 out of 46560 3%Number used as Logic: 1746 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1802Number with an unused Flip Flop: 1123 out of 1802 62%Number with an unused LUT: 56 out of 1802 3%Number of fully used LUT-FF pairs: 623 out of 1802 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.490| 8.693| 2.120| 0.530|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 679 out of 93120 0%Number of Slice LUTs: 1737 out of 46560 3%Number used as Logic: 1737 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1793Number with an unused Flip Flop: 1114 out of 1793 62%Number with an unused LUT: 56 out of 1793 3%Number of fully used LUT-FF pairs: 623 out of 1793 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.359| 7.297| 1.747| 0.520|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 679 out of 93120 0%Number of Slice LUTs: 1737 out of 46560 3%Number used as Logic: 1737 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1793Number with an unused Flip Flop: 1114 out of 1793 62%Number with an unused LUT: 56 out of 1793 3%Number of fully used LUT-FF pairs: 623 out of 1793 34%Number of unique control sets: 61IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 52.754| 25.719| | 1.573|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1322 out of 3584 36%Number of Slice Flip Flops: 721 out of 7168 10%Number of 4 input LUTs: 2366 out of 7168 33%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 46.221| 21.960| | 1.361|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1323 out of 3584 36%Number of Slice Flip Flops: 721 out of 7168 10%Number of 4 input LUTs: 2367 out of 7168 33%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 48.773| 23.787| | 1.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1329 out of 4656 28%Number of Slice Flip Flops: 721 out of 9312 7%Number of 4 input LUTs: 2383 out of 9312 25%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 42.392| 20.984| | 1.475|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1329 out of 4656 28%Number of Slice Flip Flops: 721 out of 9312 7%Number of 4 input LUTs: 2383 out of 9312 25%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 49.972| 25.346| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1338 out of 5888 22%Number of Slice Flip Flops: 722 out of 11776 6%Number of 4 input LUTs: 2396 out of 11776 20%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 43.331| 22.040| | 1.215|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1333 out of 5888 22%Number of Slice Flip Flops: 722 out of 11776 6%Number of 4 input LUTs: 2388 out of 11776 20%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 50.455| 24.701| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1343 out of 16640 8%Number of Slice Flip Flops: 722 out of 33280 2%Number of 4 input LUTs: 2402 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.805| 20.761| | 1.302|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1343 out of 16640 8%Number of Slice Flip Flops: 722 out of 33280 2%Number of 4 input LUTs: 2400 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.545| 19.046| 3.890| 2.332|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 722 out of 54576 1%Number of Slice LUTs: 1851 out of 27288 6%Number used as Logic: 1851 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1924Number with an unused Flip Flop: 1202 out of 1924 62%Number with an unused LUT: 73 out of 1924 3%Number of fully used LUT-FF pairs: 649 out of 1924 33%Number of unique control sets: 65IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.257| 15.691| 3.516| 2.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 722 out of 54576 1%Number of Slice LUTs: 1829 out of 27288 6%Number used as Logic: 1829 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1902Number with an unused Flip Flop: 1180 out of 1902 62%Number with an unused LUT: 73 out of 1902 3%Number of fully used LUT-FF pairs: 649 out of 1902 34%Number of unique control sets: 65IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 26.058| 12.330| 3.145| 1.813|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 722 out of 54576 1%Number of Slice LUTs: 1828 out of 27288 6%Number used as Logic: 1828 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1901Number with an unused Flip Flop: 1179 out of 1901 62%Number with an unused LUT: 73 out of 1901 3%Number of fully used LUT-FF pairs: 649 out of 1901 34%Number of unique control sets: 65IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 35.320| 17.572| | 0.943|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1338 out of 10752 12%Number of Slice Flip Flops: 722 out of 21504 3%Number of 4 input LUTs: 2395 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 28.130| 14.160| | 0.807|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1339 out of 10752 12%Number of Slice Flip Flops: 722 out of 21504 3%Number of 4 input LUTs: 2396 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 27.704| 13.422| | 0.717|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1338 out of 10752 12%Number of Slice Flip Flops: 722 out of 21504 3%Number of 4 input LUTs: 2394 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.632| 10.345| | 0.804|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 721 out of 19200 3%Number of Slice LUTs: 1832 out of 19200 9%Number used as Logic: 1832 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1905Number with an unused Flip Flop: 1184 out of 1905 62%Number with an unused LUT: 73 out of 1905 3%Number of fully used LUT-FF pairs: 648 out of 1905 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.682| 8.867| | 0.703|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 721 out of 19200 3%Number of Slice LUTs: 1831 out of 19200 9%Number used as Logic: 1831 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1904Number with an unused Flip Flop: 1183 out of 1904 62%Number with an unused LUT: 73 out of 1904 3%Number of fully used LUT-FF pairs: 648 out of 1904 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.053| 8.002| | 0.601|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 721 out of 19200 3%Number of Slice LUTs: 1831 out of 19200 9%Number used as Logic: 1831 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1904Number with an unused Flip Flop: 1183 out of 1904 62%Number with an unused LUT: 73 out of 1904 3%Number of fully used LUT-FF pairs: 648 out of 1904 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.604| 9.337| 2.737| 0.591|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 721 out of 93120 0%Number of Slice LUTs: 1818 out of 46560 3%Number used as Logic: 1818 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1890Number with an unused Flip Flop: 1169 out of 1890 61%Number with an unused LUT: 72 out of 1890 3%Number of fully used LUT-FF pairs: 649 out of 1890 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.834| 8.854| 1.885| 0.530|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 721 out of 93120 0%Number of Slice LUTs: 1816 out of 46560 3%Number used as Logic: 1816 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1888Number with an unused Flip Flop: 1167 out of 1888 61%Number with an unused LUT: 72 out of 1888 3%Number of fully used LUT-FF pairs: 649 out of 1888 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.418| 6.976| 1.945| 0.791|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 721 out of 93120 0%Number of Slice LUTs: 1815 out of 46560 3%Number used as Logic: 1815 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1887Number with an unused Flip Flop: 1166 out of 1887 61%Number with an unused LUT: 72 out of 1887 3%Number of fully used LUT-FF pairs: 649 out of 1887 34%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 52.228| 25.655| | 1.564|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1370 out of 3584 38%Number of Slice Flip Flops: 763 out of 7168 10%Number of 4 input LUTs: 2458 out of 7168 34%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 47.015| 21.993| | 1.361|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1371 out of 3584 38%Number of Slice Flip Flops: 763 out of 7168 10%Number of 4 input LUTs: 2459 out of 7168 34%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%IOB Flip Flops: 8Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 52.731| 25.844| | 1.649|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1380 out of 4656 29%Number of Slice Flip Flops: 763 out of 9312 8%Number of 4 input LUTs: 2474 out of 9312 26%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 46.301| 22.868| | 1.276|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1380 out of 4656 29%Number of Slice Flip Flops: 763 out of 9312 8%Number of 4 input LUTs: 2474 out of 9312 26%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%IOB Flip Flops: 8Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 52.651| 26.184| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1389 out of 5888 23%Number of Slice Flip Flops: 764 out of 11776 6%Number of 4 input LUTs: 2489 out of 11776 21%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 45.027| 22.345| | 1.192|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1385 out of 5888 23%Number of Slice Flip Flops: 764 out of 11776 6%Number of 4 input LUTs: 2483 out of 11776 21%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%IOB Flip Flops: 8Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 53.430| 26.704| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1396 out of 16640 8%Number of Slice Flip Flops: 764 out of 33280 2%Number of 4 input LUTs: 2497 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 43.087| 21.070| | 1.054|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1394 out of 16640 8%Number of Slice Flip Flops: 764 out of 33280 2%Number of 4 input LUTs: 2495 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%IOB Flip Flops: 8Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 42.798| 21.477| 4.280| 2.401|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 764 out of 54576 1%Number of Slice LUTs: 1905 out of 27288 6%Number used as Logic: 1905 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1995Number with an unused Flip Flop: 1231 out of 1995 61%Number with an unused LUT: 90 out of 1995 4%Number of fully used LUT-FF pairs: 674 out of 1995 33%Number of unique control sets: 68IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.947| 17.341| 4.440| 1.523|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 764 out of 54576 1%Number of Slice LUTs: 1876 out of 27288 6%Number used as Logic: 1876 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1965Number with an unused Flip Flop: 1201 out of 1965 61%Number with an unused LUT: 89 out of 1965 4%Number of fully used LUT-FF pairs: 675 out of 1965 34%Number of unique control sets: 68IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 25.947| 12.651| 2.499| 1.393|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 764 out of 54576 1%Number of Slice LUTs: 1873 out of 27288 6%Number used as Logic: 1873 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1962Number with an unused Flip Flop: 1198 out of 1962 61%Number with an unused LUT: 89 out of 1962 4%Number of fully used LUT-FF pairs: 675 out of 1962 34%Number of unique control sets: 68IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.919| 17.928| | 1.112|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1390 out of 10752 12%Number of Slice Flip Flops: 764 out of 21504 3%Number of 4 input LUTs: 2490 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.250| 14.353| | 0.807|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1390 out of 10752 12%Number of Slice Flip Flops: 764 out of 21504 3%Number of 4 input LUTs: 2491 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 27.322| 13.405| | 0.914|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1390 out of 10752 12%Number of Slice Flip Flops: 764 out of 21504 3%Number of 4 input LUTs: 2489 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops: 8Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.123| 10.740| | 0.971|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 763 out of 19200 3%Number of Slice LUTs: 1881 out of 19200 9%Number used as Logic: 1881 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1968Number with an unused Flip Flop: 1205 out of 1968 61%Number with an unused LUT: 87 out of 1968 4%Number of fully used LUT-FF pairs: 676 out of 1968 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.586| 8.843| | 0.688|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 763 out of 19200 3%Number of Slice LUTs: 1881 out of 19200 9%Number used as Logic: 1881 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1968Number with an unused Flip Flop: 1205 out of 1968 61%Number with an unused LUT: 87 out of 1968 4%Number of fully used LUT-FF pairs: 676 out of 1968 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.288| 8.115| | 0.641|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 763 out of 19200 3%Number of Slice LUTs: 1882 out of 19200 9%Number used as Logic: 1882 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1969Number with an unused Flip Flop: 1206 out of 1969 61%Number with an unused LUT: 87 out of 1969 4%Number of fully used LUT-FF pairs: 676 out of 1969 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.783| 9.311| 2.378| 0.606|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 763 out of 93120 0%Number of Slice LUTs: 1866 out of 46560 4%Number used as Logic: 1866 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1954Number with an unused Flip Flop: 1191 out of 1954 60%Number with an unused LUT: 88 out of 1954 4%Number of fully used LUT-FF pairs: 675 out of 1954 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.497| 8.056| 2.484| 0.530|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 763 out of 93120 0%Number of Slice LUTs: 1860 out of 46560 3%Number used as Logic: 1860 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1948Number with an unused Flip Flop: 1185 out of 1948 60%Number with an unused LUT: 88 out of 1948 4%Number of fully used LUT-FF pairs: 675 out of 1948 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (AREA optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.988| 8.110| 1.485| 0.729|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 763 out of 93120 0%Number of Slice LUTs: 1860 out of 46560 3%Number used as Logic: 1860 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1948Number with an unused Flip Flop: 1185 out of 1948 60%Number with an unused LUT: 88 out of 1948 4%Number of fully used LUT-FF pairs: 675 out of 1948 34%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%IOB Flip Flops/Latches: 8Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE#####################################################################################
Go to most recent revision | Compare with Previous | Blame | View Log