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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.speed.log] - Rev 101
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###################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.265| | | 1.564|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 923 out of 3584 25%Number of Slice Flip Flops: 477 out of 7168 6%Number of 4 input LUTs: 1761 out of 7168 24%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.586| | | 1.361|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 920 out of 3584 25%Number of Slice Flip Flops: 477 out of 7168 6%Number of 4 input LUTs: 1755 out of 7168 24%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.219| | | 1.815|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 946 out of 4656 20%Number of Slice Flip Flops: 477 out of 9312 5%Number of 4 input LUTs: 1799 out of 9312 19%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 26.827| | | 1.276|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 946 out of 4656 20%Number of Slice Flip Flops: 477 out of 9312 5%Number of 4 input LUTs: 1800 out of 9312 19%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.020| | | 1.260|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 930 out of 5888 15%Number of Slice Flip Flops: 480 out of 11776 4%Number of 4 input LUTs: 1769 out of 11776 15%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 27.706| | | 1.235|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 924 out of 5888 15%Number of Slice Flip Flops: 474 out of 11776 4%Number of 4 input LUTs: 1759 out of 11776 14%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.066| | | 1.723|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 942 out of 16640 5%Number of Slice Flip Flops: 479 out of 33280 1%Number of 4 input LUTs: 1782 out of 33280 5%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 25.434| | | 1.235|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 927 out of 16640 5%Number of Slice Flip Flops: 479 out of 33280 1%Number of 4 input LUTs: 1760 out of 33280 5%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.353| 6.455| 2.777| 1.423|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 468 out of 54576 0%Number of Slice LUTs: 1564 out of 27288 5%Number used as Logic: 1564 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1655Number with an unused Flip Flop: 1187 out of 1655 71%Number with an unused LUT: 91 out of 1655 5%Number of fully used LUT-FF pairs: 377 out of 1655 22%Number of unique control sets: 43IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.186| 5.614| 2.121| 2.181|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 465 out of 54576 0%Number of Slice LUTs: 1605 out of 27288 5%Number used as Logic: 1605 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1682Number with an unused Flip Flop: 1217 out of 1682 72%Number with an unused LUT: 77 out of 1682 4%Number of fully used LUT-FF pairs: 388 out of 1682 23%Number of unique control sets: 42IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.161| 5.201| 1.755| 1.839|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 465 out of 54576 0%Number of Slice LUTs: 1582 out of 27288 5%Number used as Logic: 1582 out of 27288 5%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1663Number with an unused Flip Flop: 1198 out of 1663 72%Number with an unused LUT: 81 out of 1663 4%Number of fully used LUT-FF pairs: 384 out of 1663 23%Number of unique control sets: 41IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.953| | | 0.932|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 934 out of 10752 8%Number of Slice Flip Flops: 474 out of 21504 2%Number of 4 input LUTs: 1773 out of 21504 8%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.461| | | 0.807|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 939 out of 10752 8%Number of Slice Flip Flops: 477 out of 21504 2%Number of 4 input LUTs: 1782 out of 21504 8%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.024| | | 0.717|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 938 out of 10752 8%Number of Slice Flip Flops: 477 out of 21504 2%Number of 4 input LUTs: 1779 out of 21504 8%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.442| | | 0.781|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 469 out of 19200 2%Number of Slice LUTs: 1488 out of 19200 7%Number used as Logic: 1488 out of 19200 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1597Number with an unused Flip Flop: 1128 out of 1597 70%Number with an unused LUT: 109 out of 1597 6%Number of fully used LUT-FF pairs: 360 out of 1597 22%Number of unique control sets: 41IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.171| | | 0.677|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 466 out of 19200 2%Number of Slice LUTs: 1445 out of 19200 7%Number used as Logic: 1445 out of 19200 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1534Number with an unused Flip Flop: 1068 out of 1534 69%Number with an unused LUT: 89 out of 1534 5%Number of fully used LUT-FF pairs: 377 out of 1534 24%Number of unique control sets: 41IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.220| | | 0.643|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 464 out of 19200 2%Number of Slice LUTs: 1447 out of 19200 7%Number used as Logic: 1447 out of 19200 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1546Number with an unused Flip Flop: 1082 out of 1546 69%Number with an unused LUT: 99 out of 1546 6%Number of fully used LUT-FF pairs: 365 out of 1546 23%Number of unique control sets: 41IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.195| 3.874| 1.642| 0.693|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 470 out of 93120 0%Number of Slice LUTs: 1549 out of 46560 3%Number used as Logic: 1549 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1599Number with an unused Flip Flop: 1129 out of 1599 70%Number with an unused LUT: 50 out of 1599 3%Number of fully used LUT-FF pairs: 420 out of 1599 26%Number of unique control sets: 41IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 9.765| 3.012| 1.436| 0.615|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 466 out of 93120 0%Number of Slice LUTs: 1474 out of 46560 3%Number used as Logic: 1474 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1517Number with an unused Flip Flop: 1051 out of 1517 69%Number with an unused LUT: 43 out of 1517 2%Number of fully used LUT-FF pairs: 423 out of 1517 27%Number of unique control sets: 42IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 0 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 8.949| 3.066| 1.224| 0.446|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 464 out of 93120 0%Number of Slice LUTs: 1451 out of 46560 3%Number used as Logic: 1451 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1487Number with an unused Flip Flop: 1023 out of 1487 68%Number with an unused LUT: 36 out of 1487 2%Number of fully used LUT-FF pairs: 428 out of 1487 28%Number of unique control sets: 42IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 35.345| 18.429| | 2.800|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1250 out of 3584 34%Number of Slice Flip Flops: 616 out of 7168 8%Number of 4 input LUTs: 2365 out of 7168 32%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.645| 15.379| | 1.809|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1252 out of 3584 34%Number of Slice Flip Flops: 617 out of 7168 8%Number of 4 input LUTs: 2367 out of 7168 33%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 35.715| 18.857| | 1.522|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1214 out of 4656 26%Number of Slice Flip Flops: 603 out of 9312 6%Number of 4 input LUTs: 2293 out of 9312 24%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.761| 15.416| | 1.727|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1214 out of 4656 26%Number of Slice Flip Flops: 603 out of 9312 6%Number of 4 input LUTs: 2293 out of 9312 24%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 34.381| 18.535| | 2.134|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1189 out of 5888 20%Number of Slice Flip Flops: 605 out of 11776 5%Number of 4 input LUTs: 2235 out of 11776 18%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.848| 15.469| | 1.719|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1232 out of 5888 20%Number of Slice Flip Flops: 606 out of 11776 5%Number of 4 input LUTs: 2322 out of 11776 19%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.891| 17.483| | 3.086|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1194 out of 16640 7%Number of Slice Flip Flops: 605 out of 33280 1%Number of 4 input LUTs: 2241 out of 33280 6%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.772| 15.569| | 1.972|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1245 out of 16640 7%Number of Slice Flip Flops: 605 out of 33280 1%Number of 4 input LUTs: 2341 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 25.580| 12.604| 7.022| 2.840|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 605 out of 54576 1%Number of Slice LUTs: 1837 out of 27288 6%Number used as Logic: 1837 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2004Number with an unused Flip Flop: 1399 out of 2004 69%Number with an unused LUT: 167 out of 2004 8%Number of fully used LUT-FF pairs: 438 out of 2004 21%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.998| 9.231| 4.222| 1.939|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 605 out of 54576 1%Number of Slice LUTs: 1785 out of 27288 6%Number used as Logic: 1785 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1906Number with an unused Flip Flop: 1301 out of 1906 68%Number with an unused LUT: 121 out of 1906 6%Number of fully used LUT-FF pairs: 484 out of 1906 25%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.427| 8.304| 4.483| 1.813|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 604 out of 54576 1%Number of Slice LUTs: 1795 out of 27288 6%Number used as Logic: 1795 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1925Number with an unused Flip Flop: 1321 out of 1925 68%Number with an unused LUT: 130 out of 1925 6%Number of fully used LUT-FF pairs: 474 out of 1925 24%Number of unique control sets: 55IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.922| 11.627| | 1.861|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1236 out of 10752 11%Number of Slice Flip Flops: 614 out of 21504 2%Number of 4 input LUTs: 2334 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.589| 9.795| | 1.905|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1235 out of 10752 11%Number of Slice Flip Flops: 614 out of 21504 2%Number of 4 input LUTs: 2332 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.402| 9.311| | 0.928|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1236 out of 10752 11%Number of Slice Flip Flops: 614 out of 21504 2%Number of 4 input LUTs: 2333 out of 21504 10%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.234| 7.556| | 0.974|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 605 out of 19200 3%Number of Slice LUTs: 1776 out of 19200 9%Number used as Logic: 1776 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1935Number with an unused Flip Flop: 1330 out of 1935 68%Number with an unused LUT: 159 out of 1935 8%Number of fully used LUT-FF pairs: 446 out of 1935 23%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.917| 6.918| | 0.709|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 607 out of 19200 3%Number of Slice LUTs: 1767 out of 19200 9%Number used as Logic: 1767 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1900Number with an unused Flip Flop: 1293 out of 1900 68%Number with an unused LUT: 133 out of 1900 7%Number of fully used LUT-FF pairs: 474 out of 1900 24%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.672| 5.947| | 1.227|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 604 out of 19200 3%Number of Slice LUTs: 1825 out of 19200 9%Number used as Logic: 1825 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1941Number with an unused Flip Flop: 1337 out of 1941 68%Number with an unused LUT: 116 out of 1941 5%Number of fully used LUT-FF pairs: 488 out of 1941 25%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.410| 5.680| 3.939| 0.973|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 605 out of 93120 0%Number of Slice LUTs: 1744 out of 46560 3%Number used as Logic: 1744 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1812Number with an unused Flip Flop: 1207 out of 1812 66%Number with an unused LUT: 68 out of 1812 3%Number of fully used LUT-FF pairs: 537 out of 1812 29%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.199| 5.125| 2.930| 1.191|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 606 out of 93120 0%Number of Slice LUTs: 1743 out of 46560 3%Number used as Logic: 1743 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1802Number with an unused Flip Flop: 1196 out of 1802 66%Number with an unused LUT: 59 out of 1802 3%Number of fully used LUT-FF pairs: 547 out of 1802 30%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 0 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 9.800| 4.522| 2.898| 0.918|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 604 out of 93120 0%Number of Slice LUTs: 1731 out of 46560 3%Number used as Logic: 1731 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1775Number with an unused Flip Flop: 1171 out of 1775 65%Number with an unused LUT: 44 out of 1775 2%Number of fully used LUT-FF pairs: 560 out of 1775 31%Number of unique control sets: 54IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 44.914| 19.434| | 3.952|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1289 out of 3584 35%Number of Slice Flip Flops: 664 out of 7168 9%Number of 4 input LUTs: 2450 out of 7168 34%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.911| 16.671| | 2.347|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1287 out of 3584 35%Number of Slice Flip Flops: 664 out of 7168 9%Number of 4 input LUTs: 2446 out of 7168 34%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.683| 17.437| | 1.757|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1340 out of 4656 28%Number of Slice Flip Flops: 659 out of 9312 7%Number of 4 input LUTs: 2542 out of 9312 27%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.921| 14.965| | 1.836|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1341 out of 4656 28%Number of Slice Flip Flops: 661 out of 9312 7%Number of 4 input LUTs: 2543 out of 9312 27%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.809| 18.679| | 1.994|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1295 out of 5888 21%Number of Slice Flip Flops: 662 out of 11776 5%Number of 4 input LUTs: 2458 out of 11776 20%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.632| 15.638| | 1.440|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1287 out of 5888 21%Number of Slice Flip Flops: 665 out of 11776 5%Number of 4 input LUTs: 2440 out of 11776 20%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.582| 18.019| | 2.349|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1308 out of 16640 7%Number of Slice Flip Flops: 661 out of 33280 1%Number of 4 input LUTs: 2475 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.668| 15.727| | 1.405|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1309 out of 16640 7%Number of Slice Flip Flops: 661 out of 33280 1%Number of 4 input LUTs: 2475 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 28.667| 13.539| 6.291| 2.666|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 650 out of 54576 1%Number of Slice LUTs: 1963 out of 27288 7%Number used as Logic: 1963 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2252Number with an unused Flip Flop: 1602 out of 2252 71%Number with an unused LUT: 289 out of 2252 12%Number of fully used LUT-FF pairs: 361 out of 2252 16%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.530| 10.191| 3.300| 2.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 648 out of 54576 1%Number of Slice LUTs: 1997 out of 27288 7%Number used as Logic: 1997 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2238Number with an unused Flip Flop: 1590 out of 2238 71%Number with an unused LUT: 241 out of 2238 10%Number of fully used LUT-FF pairs: 407 out of 2238 18%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.564| 8.450| 3.090| 1.780|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 647 out of 54576 1%Number of Slice LUTs: 1993 out of 27288 7%Number used as Logic: 1993 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2273Number with an unused Flip Flop: 1626 out of 2273 71%Number with an unused LUT: 280 out of 2273 12%Number of fully used LUT-FF pairs: 367 out of 2273 16%Number of unique control sets: 58IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 22.936| 11.389| | 0.991|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1291 out of 10752 12%Number of Slice Flip Flops: 669 out of 21504 3%Number of 4 input LUTs: 2453 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.482| 10.061| | 1.043|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1297 out of 10752 12%Number of Slice Flip Flops: 666 out of 21504 3%Number of 4 input LUTs: 2463 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.872| 8.361| | 1.448|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1295 out of 10752 12%Number of Slice Flip Flops: 664 out of 21504 3%Number of 4 input LUTs: 2458 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.850| 7.763| | 0.968|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 653 out of 19200 3%Number of Slice LUTs: 1931 out of 19200 10%Number used as Logic: 1931 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2200Number with an unused Flip Flop: 1547 out of 2200 70%Number with an unused LUT: 269 out of 2200 12%Number of fully used LUT-FF pairs: 384 out of 2200 17%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.479| 6.626| | 0.808|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 653 out of 19200 3%Number of Slice LUTs: 1930 out of 19200 10%Number used as Logic: 1930 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2169Number with an unused Flip Flop: 1516 out of 2169 69%Number with an unused LUT: 239 out of 2169 11%Number of fully used LUT-FF pairs: 414 out of 2169 19%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.826| 6.662| | 0.598|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 645 out of 19200 3%Number of Slice LUTs: 1914 out of 19200 9%Number used as Logic: 1914 out of 19200 9%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2169Number with an unused Flip Flop: 1524 out of 2169 70%Number with an unused LUT: 255 out of 2169 11%Number of fully used LUT-FF pairs: 390 out of 2169 17%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.580| 6.885| 2.742| 1.067|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 651 out of 93120 0%Number of Slice LUTs: 1902 out of 46560 4%Number used as Logic: 1902 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2031Number with an unused Flip Flop: 1380 out of 2031 67%Number with an unused LUT: 129 out of 2031 6%Number of fully used LUT-FF pairs: 522 out of 2031 25%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.529| 5.015| 2.160| 0.508|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 648 out of 93120 0%Number of Slice LUTs: 1871 out of 46560 4%Number used as Logic: 1871 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1978Number with an unused Flip Flop: 1330 out of 1978 67%Number with an unused LUT: 107 out of 1978 5%Number of fully used LUT-FF pairs: 541 out of 1978 27%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 0 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.245| 5.248| 2.230| 0.869|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 645 out of 93120 0%Number of Slice LUTs: 1849 out of 46560 3%Number used as Logic: 1849 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1943Number with an unused Flip Flop: 1298 out of 1943 66%Number with an unused LUT: 94 out of 1943 4%Number of fully used LUT-FF pairs: 551 out of 1943 28%Number of unique control sets: 57IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.083| 19.525| | 2.462|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1364 out of 3584 38%Number of Slice Flip Flops: 705 out of 7168 9%Number of 4 input LUTs: 2587 out of 7168 36%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 34.597| 16.374| | 2.028|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1363 out of 3584 38%Number of Slice Flip Flops: 703 out of 7168 9%Number of 4 input LUTs: 2582 out of 7168 36%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.723| 17.550| | 1.704|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1375 out of 4656 29%Number of Slice Flip Flops: 704 out of 9312 7%Number of 4 input LUTs: 2598 out of 9312 27%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.892| 16.075| | 1.531|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1374 out of 4656 29%Number of Slice Flip Flops: 704 out of 9312 7%Number of 4 input LUTs: 2600 out of 9312 27%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.898| 18.834| | 2.651|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1366 out of 5888 23%Number of Slice Flip Flops: 705 out of 11776 5%Number of 4 input LUTs: 2579 out of 11776 21%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.481| 16.177| | 1.899|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1363 out of 5888 23%Number of Slice Flip Flops: 702 out of 11776 5%Number of 4 input LUTs: 2567 out of 11776 21%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.761| 18.799| | 2.703|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1399 out of 16640 8%Number of Slice Flip Flops: 703 out of 33280 2%Number of 4 input LUTs: 2644 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 30.304| 15.692| | 2.161|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1393 out of 16640 8%Number of Slice Flip Flops: 702 out of 33280 2%Number of 4 input LUTs: 2624 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.068| 13.044| 5.203| 2.681|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 694 out of 54576 1%Number of Slice LUTs: 2065 out of 27288 7%Number used as Logic: 2065 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2394Number with an unused Flip Flop: 1700 out of 2394 71%Number with an unused LUT: 329 out of 2394 13%Number of fully used LUT-FF pairs: 365 out of 2394 15%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.814| 10.080| 3.646| 2.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 689 out of 54576 1%Number of Slice LUTs: 2015 out of 27288 7%Number used as Logic: 2015 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2307Number with an unused Flip Flop: 1618 out of 2307 70%Number with an unused LUT: 292 out of 2307 12%Number of fully used LUT-FF pairs: 397 out of 2307 17%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.974| 8.376| 3.701| 1.950|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 689 out of 54576 1%Number of Slice LUTs: 2022 out of 27288 7%Number used as Logic: 2022 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2362Number with an unused Flip Flop: 1673 out of 2362 70%Number with an unused LUT: 340 out of 2362 14%Number of fully used LUT-FF pairs: 349 out of 2362 14%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.000| 11.966| | 1.676|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1345 out of 10752 12%Number of Slice Flip Flops: 707 out of 21504 3%Number of 4 input LUTs: 2552 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.580| 10.256| | 0.832|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1352 out of 10752 12%Number of Slice Flip Flops: 711 out of 21504 3%Number of 4 input LUTs: 2565 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.686| 9.406| | 0.747|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1348 out of 10752 12%Number of Slice Flip Flops: 708 out of 21504 3%Number of 4 input LUTs: 2557 out of 21504 11%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 16.698| 7.658| | 0.969|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 696 out of 19200 3%Number of Slice LUTs: 1979 out of 19200 10%Number used as Logic: 1979 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2269Number with an unused Flip Flop: 1573 out of 2269 69%Number with an unused LUT: 290 out of 2269 12%Number of fully used LUT-FF pairs: 406 out of 2269 17%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.386| 6.898| | 1.121|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 695 out of 19200 3%Number of Slice LUTs: 1982 out of 19200 10%Number used as Logic: 1982 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2257Number with an unused Flip Flop: 1562 out of 2257 69%Number with an unused LUT: 275 out of 2257 12%Number of fully used LUT-FF pairs: 420 out of 2257 18%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.988| 6.250| | 0.606|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 687 out of 19200 3%Number of Slice LUTs: 1957 out of 19200 10%Number used as Logic: 1957 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2238Number with an unused Flip Flop: 1551 out of 2238 69%Number with an unused LUT: 281 out of 2238 12%Number of fully used LUT-FF pairs: 406 out of 2238 18%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.982| 6.215| 3.219| 0.798|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 692 out of 93120 0%Number of Slice LUTs: 1949 out of 46560 4%Number used as Logic: 1949 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2113Number with an unused Flip Flop: 1421 out of 2113 67%Number with an unused LUT: 164 out of 2113 7%Number of fully used LUT-FF pairs: 528 out of 2113 24%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.508| 5.907| 2.273| 1.135|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 691 out of 93120 0%Number of Slice LUTs: 1942 out of 46560 4%Number used as Logic: 1942 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2099Number with an unused Flip Flop: 1408 out of 2099 67%Number with an unused LUT: 157 out of 2099 7%Number of fully used LUT-FF pairs: 534 out of 2099 25%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 0 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.123| 5.148| 2.809| 0.757|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 688 out of 93120 0%Number of Slice LUTs: 1911 out of 46560 4%Number used as Logic: 1911 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2050Number with an unused Flip Flop: 1362 out of 2050 66%Number with an unused LUT: 139 out of 2050 6%Number of fully used LUT-FF pairs: 549 out of 2050 26%Number of unique control sets: 60IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 39.704| 19.787| | 3.074|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1407 out of 3584 39%Number of Slice Flip Flops: 745 out of 7168 10%Number of 4 input LUTs: 2665 out of 7168 37%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.126| 17.381| | 2.467|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1408 out of 3584 39%Number of Slice Flip Flops: 749 out of 7168 10%Number of 4 input LUTs: 2666 out of 7168 37%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.551| 18.269| | 1.541|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1413 out of 4656 30%Number of Slice Flip Flops: 740 out of 9312 7%Number of 4 input LUTs: 2673 out of 9312 28%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.042| 16.542| | 1.590|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1414 out of 4656 30%Number of Slice Flip Flops: 740 out of 9312 7%Number of 4 input LUTs: 2675 out of 9312 28%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 40.202| 20.226| | 1.744|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1392 out of 5888 23%Number of Slice Flip Flops: 744 out of 11776 6%Number of 4 input LUTs: 2630 out of 11776 22%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.669| 16.672| | 1.350|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1400 out of 5888 23%Number of Slice Flip Flops: 749 out of 11776 6%Number of 4 input LUTs: 2654 out of 11776 22%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 41.154| 19.523| | 1.712|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1393 out of 16640 8%Number of Slice Flip Flops: 743 out of 33280 2%Number of 4 input LUTs: 2631 out of 33280 7%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 34.646| 17.254| | 1.440|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1411 out of 16640 8%Number of Slice Flip Flops: 743 out of 33280 2%Number of 4 input LUTs: 2666 out of 33280 8%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 37.179| 16.588| 5.255| 2.769|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 733 out of 54576 1%Number of Slice LUTs: 2129 out of 27288 7%Number used as Logic: 2129 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2484Number with an unused Flip Flop: 1751 out of 2484 70%Number with an unused LUT: 355 out of 2484 14%Number of fully used LUT-FF pairs: 378 out of 2484 15%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.944| 10.602| 4.122| 2.062|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 731 out of 54576 1%Number of Slice LUTs: 2069 out of 27288 7%Number used as Logic: 2069 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2455Number with an unused Flip Flop: 1724 out of 2455 70%Number with an unused LUT: 386 out of 2455 15%Number of fully used LUT-FF pairs: 345 out of 2455 14%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.273| 9.827| 4.275| 1.961|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 732 out of 54576 1%Number of Slice LUTs: 2077 out of 27288 7%Number used as Logic: 2077 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2435Number with an unused Flip Flop: 1703 out of 2435 69%Number with an unused LUT: 358 out of 2435 14%Number of fully used LUT-FF pairs: 374 out of 2435 15%Number of unique control sets: 64IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.616| 11.532| | 1.218|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1401 out of 10752 13%Number of Slice Flip Flops: 744 out of 21504 3%Number of 4 input LUTs: 2653 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 20.532| 10.117| | 1.215|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1383 out of 10752 12%Number of Slice Flip Flops: 746 out of 21504 3%Number of 4 input LUTs: 2615 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.383| 8.899| | 1.262|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1384 out of 10752 12%Number of Slice Flip Flops: 748 out of 21504 3%Number of 4 input LUTs: 2618 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.869| 8.889| | 0.874|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 736 out of 19200 3%Number of Slice LUTs: 2075 out of 19200 10%Number used as Logic: 2075 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2470Number with an unused Flip Flop: 1734 out of 2470 70%Number with an unused LUT: 395 out of 2470 15%Number of fully used LUT-FF pairs: 341 out of 2470 13%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.123| 8.222| | 1.070|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 735 out of 19200 3%Number of Slice LUTs: 2035 out of 19200 10%Number used as Logic: 2035 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2337Number with an unused Flip Flop: 1602 out of 2337 68%Number with an unused LUT: 302 out of 2337 12%Number of fully used LUT-FF pairs: 433 out of 2337 18%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.045| 6.978| | 0.992|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 730 out of 19200 3%Number of Slice LUTs: 2024 out of 19200 10%Number used as Logic: 2024 out of 19200 10%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2376Number with an unused Flip Flop: 1646 out of 2376 69%Number with an unused LUT: 352 out of 2376 14%Number of fully used LUT-FF pairs: 378 out of 2376 15%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.595| 6.668| 2.831| 1.136|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 734 out of 93120 0%Number of Slice LUTs: 2030 out of 46560 4%Number used as Logic: 2030 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2217Number with an unused Flip Flop: 1483 out of 2217 66%Number with an unused LUT: 187 out of 2217 8%Number of fully used LUT-FF pairs: 547 out of 2217 24%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.954| 6.088| 2.275| 0.666|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 732 out of 93120 0%Number of Slice LUTs: 2050 out of 46560 4%Number used as Logic: 2050 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2228Number with an unused Flip Flop: 1496 out of 2228 67%Number with an unused LUT: 178 out of 2228 7%Number of fully used LUT-FF pairs: 554 out of 2228 24%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 0#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.838| 5.749| 1.970| 0.610|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 730 out of 93120 0%Number of Slice LUTs: 1989 out of 46560 4%Number used as Logic: 1989 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2160Number with an unused Flip Flop: 1430 out of 2160 66%Number with an unused LUT: 171 out of 2160 7%Number of fully used LUT-FF pairs: 559 out of 2160 25%Number of unique control sets: 63IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 42.561| 19.205| | 1.728|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1463 out of 3584 40%Number of Slice Flip Flops: 789 out of 7168 11%Number of 4 input LUTs: 2781 out of 7168 38%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.184| 16.807| | 1.469|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1462 out of 3584 40%Number of Slice Flip Flops: 789 out of 7168 11%Number of 4 input LUTs: 2780 out of 7168 38%Number of IOs: 80Number of bonded IOBs: 80 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 40.325| 18.287| | 1.769|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1461 out of 4656 31%Number of Slice Flip Flops: 788 out of 9312 8%Number of 4 input LUTs: 2775 out of 9312 29%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 34.139| 15.738| | 1.663|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1456 out of 4656 31%Number of Slice Flip Flops: 788 out of 9312 8%Number of 4 input LUTs: 2763 out of 9312 29%Number of IOs: 80Number of bonded IOBs: 80 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 40.868| 20.027| | 1.646|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1444 out of 5888 24%Number of Slice Flip Flops: 786 out of 11776 6%Number of 4 input LUTs: 2736 out of 11776 23%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 36.100| 17.592| | 1.473|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1446 out of 5888 24%Number of Slice Flip Flops: 790 out of 11776 6%Number of 4 input LUTs: 2739 out of 11776 23%Number of IOs: 80Number of bonded IOBs: 80 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 40.711| 20.043| | 1.600|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1473 out of 16640 8%Number of Slice Flip Flops: 785 out of 33280 2%Number of 4 input LUTs: 2791 out of 33280 8%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 35.096| 17.864| | 2.215|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1485 out of 16640 8%Number of Slice Flip Flops: 787 out of 33280 2%Number of 4 input LUTs: 2810 out of 33280 8%Number of IOs: 80Number of bonded IOBs: 80 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.530| 14.036| 7.081| 2.770|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 777 out of 54576 1%Number of Slice LUTs: 2187 out of 27288 8%Number used as Logic: 2187 out of 27288 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2579Number with an unused Flip Flop: 1802 out of 2579 69%Number with an unused LUT: 392 out of 2579 15%Number of fully used LUT-FF pairs: 385 out of 2579 14%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 23.080| 10.700| 2.690| 2.071|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 773 out of 54576 1%Number of Slice LUTs: 2112 out of 27288 7%Number used as Logic: 2112 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2548Number with an unused Flip Flop: 1775 out of 2548 69%Number with an unused LUT: 436 out of 2548 17%Number of fully used LUT-FF pairs: 337 out of 2548 13%Number of unique control sets: 67IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 22.929| 8.541| 3.393| 1.743|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 774 out of 54576 1%Number of Slice LUTs: 2123 out of 27288 7%Number used as Logic: 2123 out of 27288 7%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2536Number with an unused Flip Flop: 1762 out of 2536 69%Number with an unused LUT: 413 out of 2536 16%Number of fully used LUT-FF pairs: 361 out of 2536 14%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 296 27%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 25.522| 11.495| | 1.677|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1462 out of 10752 13%Number of Slice Flip Flops: 794 out of 21504 3%Number of 4 input LUTs: 2779 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 21.103| 10.381| | 0.851|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1464 out of 10752 13%Number of Slice Flip Flops: 792 out of 21504 3%Number of 4 input LUTs: 2781 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.563| 8.688| | 0.748|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1461 out of 10752 13%Number of Slice Flip Flops: 793 out of 21504 3%Number of 4 input LUTs: 2775 out of 21504 12%Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 18.680| 8.472| | 1.313|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 774 out of 19200 4%Number of Slice LUTs: 2170 out of 19200 11%Number used as Logic: 2170 out of 19200 11%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2589Number with an unused Flip Flop: 1815 out of 2589 70%Number with an unused LUT: 419 out of 2589 16%Number of fully used LUT-FF pairs: 355 out of 2589 13%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.274| 6.394| | 0.680|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 773 out of 19200 4%Number of Slice LUTs: 2173 out of 19200 11%Number used as Logic: 2173 out of 19200 11%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2509Number with an unused Flip Flop: 1736 out of 2509 69%Number with an unused LUT: 336 out of 2509 13%Number of fully used LUT-FF pairs: 437 out of 2509 17%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.481| 6.419| | 0.605|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 771 out of 19200 4%Number of Slice LUTs: 2143 out of 19200 11%Number used as Logic: 2143 out of 19200 11%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2571Number with an unused Flip Flop: 1800 out of 2571 70%Number with an unused LUT: 428 out of 2571 16%Number of fully used LUT-FF pairs: 343 out of 2571 13%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 220 36%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.044| 6.354| 2.500| 1.022|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 776 out of 93120 0%Number of Slice LUTs: 2043 out of 46560 4%Number used as Logic: 2043 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2266Number with an unused Flip Flop: 1490 out of 2266 65%Number with an unused LUT: 223 out of 2266 9%Number of fully used LUT-FF pairs: 553 out of 2266 24%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.344| 6.146| 2.734| 0.906|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 774 out of 93120 0%Number of Slice LUTs: 2071 out of 46560 4%Number used as Logic: 2071 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2284Number with an unused Flip Flop: 1510 out of 2284 66%Number with an unused LUT: 213 out of 2284 9%Number of fully used LUT-FF pairs: 561 out of 2284 24%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3# 12 10 1 1 1 1 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 11.013| 5.057| 1.808| 0.463|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 771 out of 93120 0%Number of Slice LUTs: 2031 out of 46560 4%Number used as Logic: 2031 out of 46560 4%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 2241Number with an unused Flip Flop: 1470 out of 2241 65%Number with an unused LUT: 210 out of 2241 9%Number of fully used LUT-FF pairs: 561 out of 2241 25%Number of unique control sets: 66IO Utilization:Number of IOs: 80Number of bonded IOBs: 80 out of 240 33%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE#####################################################################################
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