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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.speed.mpy.log] - Rev 74
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###################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 33.283| | | 1.675|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4Number of Slices: 1030 out of 3584 28%Number of Slice Flip Flops: 548 out of 7168 7%Number of 4 input LUTs: 1967 out of 7168 27%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of MULT18X18s: 1 out of 16 6%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3 (xc3s400pq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 29.319| | | 1.687|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5Number of Slices: 1028 out of 3584 28%Number of Slice Flip Flops: 546 out of 7168 7%Number of 4 input LUTs: 1965 out of 7168 27%Number of IOs: 80Number of bonded IOBs: 79 out of 141 56%Number of BRAMs: 6 out of 16 37%Number of MULT18X18s: 1 out of 16 6%Number of GCLKs: 1 out of 8 12%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.162| | | 1.457|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-4Number of Slices: 1054 out of 4656 22%Number of Slice Flip Flops: 548 out of 9312 5%Number of 4 input LUTs: 2007 out of 9312 21%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of MULT18X18SIOs: 1 out of 20 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3e (xc3s500epq208), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 26.516| | | 1.819|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s500epq208-5Number of Slices: 1054 out of 4656 22%Number of Slice Flip Flops: 548 out of 9312 5%Number of 4 input LUTs: 2008 out of 9312 21%Number of IOs: 80Number of bonded IOBs: 79 out of 158 50%Number of BRAMs: 6 out of 20 30%Number of MULT18X18SIOs: 1 out of 20 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 32.202| | | 2.032|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-4Number of Slices: 1035 out of 5888 17%Number of Slice Flip Flops: 551 out of 11776 4%Number of 4 input LUTs: 1972 out of 11776 16%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of MULT18X18SIOs: 1 out of 20 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3a (xc3s700aft256), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 27.667| | | 1.760|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3s700aft256-5Number of Slices: 1031 out of 5888 17%Number of Slice Flip Flops: 543 out of 11776 4%Number of 4 input LUTs: 1965 out of 11776 16%Number of IOs: 80Number of bonded IOBs: 79 out of 161 49%Number of BRAMs: 5 out of 20 25%Number of MULT18X18SIOs: 1 out of 20 5%Number of GCLKs: 1 out of 24 4%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 31.993| | | 2.000|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-4Number of Slices: 1049 out of 16640 6%Number of Slice Flip Flops: 549 out of 33280 1%Number of 4 input LUTs: 1988 out of 33280 5%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%Number of DSP48s: 1 out of 84 1%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan3adsp (xc3sd1800acs484), speedgrade: -5#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 26.605| | | 1.346|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 3sd1800acs484-5Number of Slices: 1034 out of 16640 6%Number of Slice Flip Flops: 550 out of 33280 1%Number of 4 input LUTs: 1967 out of 33280 5%Number of IOs: 80Number of bonded IOBs: 79 out of 309 25%Number of BRAMs: 5 out of 84 5%Number of GCLKs: 1 out of 24 4%Number of DSP48s: 1 out of 84 1%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 24.371| 6.986| 3.176| 2.681|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-2Slice Logic Utilization:Number of Slice Registers: 537 out of 54576 0%Number of Slice LUTs: 1714 out of 27288 6%Number used as Logic: 1714 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1827Number with an unused Flip Flop: 1290 out of 1827 70%Number with an unused LUT: 113 out of 1827 6%Number of fully used LUT-FF pairs: 424 out of 1827 23%Number of unique control sets: 46IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%Number of DSP48A1s: 1 out of 58 1%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.180| 5.946| 2.019| 1.844|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-3Slice Logic Utilization:Number of Slice Registers: 535 out of 54576 0%Number of Slice LUTs: 1740 out of 27288 6%Number used as Logic: 1740 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1836Number with an unused Flip Flop: 1301 out of 1836 70%Number with an unused LUT: 96 out of 1836 5%Number of fully used LUT-FF pairs: 439 out of 1836 23%Number of unique control sets: 48IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%Number of DSP48A1s: 1 out of 58 1%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# spartan6 (xc6slx45tfgg484), speedgrade: -4#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 14.789| 4.575| 2.236| 1.813|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6slx45tfgg484-4Slice Logic Utilization:Number of Slice Registers: 535 out of 54576 0%Number of Slice LUTs: 1815 out of 27288 6%Number used as Logic: 1815 out of 27288 6%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1933Number with an unused Flip Flop: 1398 out of 1933 72%Number with an unused LUT: 118 out of 1933 6%Number of fully used LUT-FF pairs: 417 out of 1933 21%Number of unique control sets: 47IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 296 26%Specific Feature Utilization:Number of Block RAM/FIFO: 5 out of 348 1%Number using Block RAM only: 5Number of BUFG/BUFGCTRLs: 1 out of 16 6%Number of DSP48A1s: 1 out of 58 1%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -10#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 19.543| | | 0.967|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10Number of Slices: 1040 out of 10752 9%Number of Slice Flip Flops: 547 out of 21504 2%Number of 4 input LUTs: 1975 out of 21504 9%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%Number of DSP48s: 1 out of 48 2%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -11#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 17.812| | | 1.014|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-11Number of Slices: 1039 out of 10752 9%Number of Slice Flip Flops: 549 out of 21504 2%Number of 4 input LUTs: 1973 out of 21504 9%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%Number of DSP48s: 1 out of 48 2%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex4 (xc4vlx25sf363), speedgrade: -12#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 15.481| | | 0.914|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-12Number of Slices: 1040 out of 10752 9%Number of Slice Flip Flops: 549 out of 21504 2%Number of 4 input LUTs: 1974 out of 21504 9%Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Number of FIFO16/RAMB16s: 5 out of 72 6%Number used as RAMB16s: 5Number of GCLKs: 1 out of 32 3%Number of DSP48s: 1 out of 48 2%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 13.389| | | 1.305|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-1Slice Logic Utilization:Number of Slice Registers: 538 out of 19200 2%Number of Slice LUTs: 1607 out of 19200 8%Number used as Logic: 1607 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1730Number with an unused Flip Flop: 1192 out of 1730 68%Number with an unused LUT: 123 out of 1730 7%Number of fully used LUT-FF pairs: 415 out of 1730 23%Number of unique control sets: 47IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48Es: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 12.178| | | 0.677|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-2Slice Logic Utilization:Number of Slice Registers: 537 out of 19200 2%Number of Slice LUTs: 1606 out of 19200 8%Number used as Logic: 1606 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1709Number with an unused Flip Flop: 1172 out of 1709 68%Number with an unused LUT: 103 out of 1709 6%Number of fully used LUT-FF pairs: 434 out of 1709 25%Number of unique control sets: 47IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48Es: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex5 (xc5vlx30ff324), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.283| | | 0.589|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 5vlx30ff324-3Slice Logic Utilization:Number of Slice Registers: 534 out of 19200 2%Number of Slice LUTs: 1590 out of 19200 8%Number used as Logic: 1590 out of 19200 8%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1680Number with an unused Flip Flop: 1146 out of 1680 68%Number with an unused LUT: 90 out of 1680 5%Number of fully used LUT-FF pairs: 444 out of 1680 26%Number of unique control sets: 47IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 220 35%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 32 9%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48Es: 1 out of 32 3%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -1#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.800| 3.353| 3.579| 0.591|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 538 out of 93120 0%Number of Slice LUTs: 1691 out of 46560 3%Number used as Logic: 1691 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1760Number with an unused Flip Flop: 1222 out of 1760 69%Number with an unused LUT: 69 out of 1760 3%Number of fully used LUT-FF pairs: 469 out of 1760 26%Number of unique control sets: 47IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48E1s: 1 out of 288 0%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -2#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 10.255| 3.286| 1.471| 0.601|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-2Slice Logic Utilization:Number of Slice Registers: 536 out of 93120 0%Number of Slice LUTs: 1613 out of 46560 3%Number used as Logic: 1613 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1678Number with an unused Flip Flop: 1142 out of 1678 68%Number with an unused LUT: 65 out of 1678 3%Number of fully used LUT-FF pairs: 471 out of 1678 28%Number of unique control sets: 48IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48E1s: 1 out of 288 0%---------------------------====================================================================================# SYNTHESIS DONE########################################################################################################################################################################### START SYNTHESIS (SPEED optimized)#====================================================================================# virtex6 (xc6vlx75tff484), speedgrade: -3#====================================================================================# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER# 12 10 0 0 0 0 0 1#====================================================================================Clock to Setup on destination clock dco_clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+dco_clk | 8.642| 3.262| 1.174| 0.518|---------------+---------+---------+---------+---------+====================================================================================Device utilization summary:---------------------------Selected Device : 6vlx75tff484-3Slice Logic Utilization:Number of Slice Registers: 534 out of 93120 0%Number of Slice LUTs: 1632 out of 46560 3%Number used as Logic: 1632 out of 46560 3%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 1690Number with an unused Flip Flop: 1156 out of 1690 68%Number with an unused LUT: 58 out of 1690 3%Number of fully used LUT-FF pairs: 476 out of 1690 28%Number of unique control sets: 48IO Utilization:Number of IOs: 80Number of bonded IOBs: 79 out of 240 32%Specific Feature Utilization:Number of Block RAM/FIFO: 3 out of 156 1%Number using Block RAM only: 3Number of BUFG/BUFGCTRLs: 1 out of 32 3%Number of DSP48E1s: 1 out of 288 0%---------------------------====================================================================================# SYNTHESIS DONE#####################################################################################
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