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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [coregen.cgp] - Rev 62

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# Date: Sat Jan 30 22:11:13 2010

SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = ./tmp/

# CRC: 4cfc2e68

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