Subversion Repositories openmsp430

# Date: Sun Jan 17 10:27:34 2010

SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = False
SET workingdirectory = ./tmp/

# CRC: af672c72