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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex4.cgp] - Rev 62

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# Date: Sun Jan 17 12:38:52 2010

SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc4vlx25
SET devicefamily = virtex4
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = sf363
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -12
SET verilogsim = True
SET vhdlsim = False
SET workingdirectory = ./tmp/

# CRC: 325d911a

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