URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex4lx.cgp] - Rev 62
Compare with Previous | Blame | View Log
# Date: Sat Jan 30 22:09:56 2010
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = ./tmp/
# CRC: 4cfc2e68