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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [src/] [coregen/] [virtex6_dmem.vho] - Rev 222
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-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
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-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component virtex6_dmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : virtex6_dmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file virtex6_dmem.vhd when simulating
-- the core, virtex6_dmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
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