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<head>
<title>openMSP430 Core</title>
</head>
<body>
<h3>Table of content</h3>
<ul>
<li><a href="#1. Introduction">1. Introduction</a></li>
<li><a href="#2. Design"> 2. Design</a>
<ul>
<li><a href="#2.1 Core"> 2.1 Core</a>
<ul>
<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
<ul>
<li><a href="#2.1.3.1 Basic System Configuration"> 2.1.3.1 Basic System Configuration</a></li>
<li><a href="#2.1.3.2 Advanced System Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
<li><a href="#2.1.3.3 Expert System Configuration"> 2.1.3.3 Expert System Configuration</a></li>
</ul>
<li><a href="#2.1.4 Memory mapping"> 2.1.4 Memory mapping</a></li>
<li><a href="#2.1.5 Pinout"> 2.1.5 Pinout</a></li>
<li><a href="#2.1.6 Instruction Cycles and Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
<li><a href="#2.1.7 Serial Debug Interface"> 2.1.7 Serial Debug Interface</a></li>
</ul>
</li>
<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
<ul>
<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
<li><a href="#2.2.2 Watchdog Timer"> 2.2.2 Watchdog Timer</a></li>
<li><a href="#2.2.3 Digital I/O"> 2.2.3 Digital I/O</a></li>
<li><a href="#2.2.4 Timer A"> 2.2.4 Timer A</a></li>
<li><a href="#2.2.5 16x16 Hardware Multiplier"> 2.2.5 16x16 Hardware Multiplier</a></li>
</ul>
</li>
</ul>
</li>
</ul>
<a name="1. Introduction"></a>
<h1>1. Introduction</h1>
The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b> (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
<br /><br />
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
<br /><br />
It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
<br /><br />
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
<br /><br />
<a name="2. Design"></a>
<h1>2. Design</h1>
<a name="2.1 Core"></a>
<h2>2.1 Core</h2>
<a name="2.1.1 Design structure"></a>
<h3>2.1.1 Design structure</h3>
The following diagram shows the openMSP430 design structure:
<br /><br />
<img src="getimg.php?1267738921" width="100%" alt="CPU Structure" title="CPU Structure" />
<br />
<ul>
<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
<li><b>16x16 Multiplier</b>: The hardware multiplier peripheral is transparently supported by the GCC compiler and is also located in the core. It can be included or excluded at will through a Verilog define.</li>
</ul>
<a name="2.1.2 Limitations"></a>
<h3>2.1.2 Limitations</h3>
The known core limitations are the following:
<br />
<ul>
<li>Instructions can't be executed from the data memory.</li>
<li>SCG0 is not implemented (turns off DCO).</li>
<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li>
</ul>
<a name="2.1.3 Configuration"></a>
<h3>2.1.3 Configuration</h3>
It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
Three sets of parameters can be adjusted by the user in order to fully customize the core.
<a name="2.1.3.1 Basic System Configuration"></a>
<h4>2.1.3.1 Basic System Configuration</h4>
The basic system can be adjusted with the following set of defines in order to match the target system requirements.
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
//============================================================================
<br />//============================================================================
<br />// BASIC SYSTEM CONFIGURATION
<br />//============================================================================
<br />//============================================================================
<br />//
<br />// Note: the sum of program, data and peripheral memory spaces must not
<br />// exceed 64 kB
<br />//
<br />
<br />// Program Memory Size:
<br />// Uncomment the required memory size
<br />//-------------------------------------------------------
<br />//`define PMEM_SIZE_59_KB
<br />//`define PMEM_SIZE_55_KB
<br />//`define PMEM_SIZE_54_KB
<br />//`define PMEM_SIZE_51_KB
<br />//`define PMEM_SIZE_48_KB
<br />//`define PMEM_SIZE_41_KB
<br />//`define PMEM_SIZE_32_KB
<br />//`define PMEM_SIZE_24_KB
<br />//`define PMEM_SIZE_16_KB
<br />//`define PMEM_SIZE_12_KB
<br />//`define PMEM_SIZE_8_KB
<br />//`define PMEM_SIZE_4_KB
<br />`define PMEM_SIZE_2_KB
<br />//`define PMEM_SIZE_1_KB
<br />
<br />// Data Memory Size:
<br />// Uncomment the required memory size
<br />//-------------------------------------------------------
<br />//`define DMEM_SIZE_32_KB
<br />//`define DMEM_SIZE_24_KB
<br />//`define DMEM_SIZE_16_KB
<br />//`define DMEM_SIZE_10_KB
<br />//`define DMEM_SIZE_8_KB
<br />//`define DMEM_SIZE_5_KB
<br />//`define DMEM_SIZE_4_KB
<br />//`define DMEM_SIZE_2p5_KB
<br />//`define DMEM_SIZE_2_KB
<br />//`define DMEM_SIZE_1_KB
<br />//`define DMEM_SIZE_512_B
<br />//`define DMEM_SIZE_256_B
<br />`define DMEM_SIZE_128_B
<br />
<br />// Include/Exclude Hardware Multiplier
<br />`define MULTIPLIER
<br />
<br />// Include/Exclude Serial Debug interface
<br />`define DBG_EN
</code>
</td>
</tr>
</table>
<br /><br />
The only design considerations at this stage are:
<ul>
<li>Make sure that the program and data memories have the correct size :-P</li>
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
</ul>
<br />
<a name="2.1.3.2 Advanced System Configuration"></a>
<h4>2.1.3.2 Advanced System Configuration</h4>
In this section, some additional features are available in order to match the needs of more experienced users.
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
//============================================================================
<br />//============================================================================
<br />// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
<br />//============================================================================
<br />//============================================================================
<br />
<br />//-------------------------------------------------------
<br />// Peripheral Memory Space:
<br />//-------------------------------------------------------
<br />// The original MSP430 architecture map the peripherals
<br />// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
<br />// The following defines allow you to expand this space
<br />// up to 32 kB (i.e. from 0x0000 to 0x7fff).
<br />// As a consequence, the data memory mapping will be
<br />// shifted up and a custom linker script will therefore
<br />// be required by the GCC compiler.
<br />//-------------------------------------------------------
<br />//`define PER_SIZE_32_KB
<br />//`define PER_SIZE_16_KB
<br />//`define PER_SIZE_8_KB
<br />//`define PER_SIZE_4_KB
<br />//`define PER_SIZE_2_KB
<br />//`define PER_SIZE_1_KB
<br />`define PER_SIZE_512_B
<br />
<br />
<br />//-------------------------------------------------------
<br />// Defines the debugger CPU_CTL.RST_BRK_EN reset value
<br />// (CPU break on PUC reset)
<br />//-------------------------------------------------------
<br />// When defined, the CPU will automatically break after
<br />// a PUC occurrence by default. This is typically usefull
<br />// when the program memory can only be initialized through
<br />// the serial debug interface.
<br />//-------------------------------------------------------
<br />//`define DBG_RST_BRK_EN
<br />
<br />
<br />//-------------------------------------------------------
<br />// Custom user version number
<br />//-------------------------------------------------------
<br />// This 5 bit field can be freely used in order to allow
<br />// custom identification of the system through the debug
<br />// interface.
<br />// (see CPU_ID.USER_VERSION field in the documentation)
<br />//-------------------------------------------------------
<br />`define USER_VERSION 5'b00000
<br />
</code>
</td>
</tr>
</table>
<br /><br />
Design consideration at this stage are:
<ul>
<li>Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.</li>
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
</ul>
<br />
<a name="2.1.3.3 Expert System Configuration"></a>
<h4>2.1.3.3 Expert System Configuration</h4>
In this section, you will find configuration options which will be relevant for roughly 0.01% of the users (according to an highly reliable market analysis ;-) ).
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
//============================================================================
<br />//============================================================================
<br />// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
<br />//============================================================================
<br />//============================================================================
<br />//
<br />// IMPORTANT NOTE: Please update following configuration options ONLY if
<br />// you have a good reason to do so... and if you know what
<br />// you are doing :-P
<br />//
<br />//============================================================================
<br />
<br />//-------------------------------------------------------
<br />// Number of hardware breakpoint units (each unit contains
<br />// two hardware address breakpoints):
<br />// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
<br />// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
<br />// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
<br />// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
<br />//-------------------------------------------------------
<br />// Please keep in mind that hardware breakpoints only
<br />// make sense whenever the program memory is not an SRAM
<br />// (i.e. Flash/OTP/ROM/...) or when you are interested
<br />// in data breakpoints (btw. not supported by GDB).
<br />//-------------------------------------------------------
<br />//`define DBG_HWBRK_0
<br />//`define DBG_HWBRK_1
<br />//`define DBG_HWBRK_2
<br />//`define DBG_HWBRK_3
<br />
<br />//-------------------------------------------------------
<br />// Enable/Disable the hardware breakpoint RANGE mode
<br />//-------------------------------------------------------
<br />// When enabled this feature allows the hardware breakpoint
<br />// units to stop the cpu whenever an instruction or data
<br />// access lays within an address range.
<br />// Note that this feature is not supported by GDB.
<br />//-------------------------------------------------------
<br />//`define DBG_HWBRK_RANGE
<br />
<br />//-------------------------------------------------------
<br />// Input synchronizers
<br />//-------------------------------------------------------
<br />// In some cases, the asynchronous input ports might
<br />// already be synchronized externally.
<br />// If an extensive CDC design review showed that this
<br />// is really the case, the individual synchronizers
<br />// can be disabled with the following defines.
<br />//
<br />// Notes:
<br />// - the dbg_en signal will reset the debug interface
<br />// when 0. Therefore make sure it is glitch free.
<br />//
<br />// - the dbg_uart_rxd synchronizer must be set to 1
<br />// when its reset is active.
<br />//-------------------------------------------------------
<br />`define SYNC_CPU_EN
<br />`define SYNC_DBG_EN
<br />`define SYNC_DBG_UART_RXD
<br />`define SYNC_NMI
<br />
</code>
</td>
</tr>
</table>
<br /><br />
Design consideration at this stage are:
<ul>
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
</ul>
<br />
All remaining defines located in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
<br /><br />
<a name="2.1.4 Memory mapping"></a>
<h3>2.1.4 Memory mapping</h3>
As discussed in the earlier section, the openMSP430 memory mapping is fully configurable.<br />
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC4 (or any other toolchain for that matter).<br />
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section give the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.<br />
The following schematic should hopefully summarize this:<br />
<br /><br />
<img src="usercontent,img,1306066277" width="100%" alt="Memory mapping" title="Memory mapping" />
<br />
<br /><br />
<a name="2.1.5 Pinout"></a>
<h3>2.1.5 Pinout</h3>
The full pinout of the openMSP430 core is provided in the following table:
<br /><br />
<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
<tr>
<td> cpu_en </td>
<td> Input </td>
<td> 1 </td>
<td> Enable CPU code execution (asynchronous) - set to 1 if unused </td>
</tr>
<tr>
<td> dco_clk </td>
<td> Input </td>
<td> 1 </td>
<td> Fast oscillator (fast clock), CPU clock </td>
</tr>
<tr>
<td> lfxt_clk </td>
<td> Input </td>
<td> 1 </td>
<td> Low frequency oscillator (typ. 32kHz) </td>
</tr>
<tr>
<td> mclk </td>
<td> Output </td>
<td> 1 </td>
<td> Main system clock </td>
</tr>
<tr>
<td> aclk_en </td>
<td> Output </td>
<td> 1 </td>
<td> ACLK enable </td>
</tr>
<tr>
<td> smclk_en </td>
<td> Output </td>
<td> 1 </td>
<td> SMCLK enable </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
<tr>
<td> puc_rst </td>
<td> Output </td>
<td> 1 </td>
<td> Main system reset </td>
</tr>
<tr>
<td> reset_n </td>
<td> Input </td>
<td> 1 </td>
<td> Reset Pin (active low, asynchronous) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
<tr>
<td> pmem_addr </td>
<td> Output </td>
<td> `PMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b> </td>
<td> Program Memory address </td>
</tr>
<tr>
<td> pmem_cen </td>
<td> Output </td>
<td> 1 </td>
<td> Program Memory chip enable (low active) </td>
</tr>
<tr>
<td> pmem_din </td>
<td> Output </td>
<td> 16 </td>
<td> Program Memory data input (optional <b><sup><font color="#FF0000">2</font></sup></b>)</td>
</tr>
<tr>
<td> pmem_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Program Memory data output </td>
</tr>
<tr>
<td> pmem_wen </td>
<td> Output </td>
<td> 2 </td>
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#FF0000">2</font></sup></b>) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
<tr>
<td> dmem_addr </td>
<td> Output </td>
<td> `DMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b></td>
<td> Data Memory address </td>
</tr>
<tr>
<td> dmem_cen </td>
<td> Output </td>
<td> 1 </td>
<td> Data Memory chip enable (low active) </td>
</tr>
<tr>
<td> dmem_din </td>
<td> Output </td>
<td> 16 </td>
<td> Data Memory data input </td>
</tr>
<tr>
<td> dmem_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Data Memory data output </td>
</tr>
<tr>
<td> dmem_wen </td>
<td> Output </td>
<td> 2 </td>
<td> Data Memory write byte enable (low active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr>
<td> per_addr </td>
<td> Output </td>
<td> 14 </td>
<td> Peripheral address </td>
</tr>
<tr>
<td> per_din </td>
<td> Output </td>
<td> 16 </td>
<td> Peripheral data input </td>
</tr>
<tr>
<td> per_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Peripheral data output </td>
</tr>
<tr>
<td> per_en </td>
<td> Output </td>
<td> 1 </td>
<td> Peripheral enable (high active) </td>
</tr>
<tr>
<td> per_we </td>
<td> Output </td>
<td> 2 </td>
<td> Peripheral write enable (high active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr>
<td> irq </td>
<td> Input </td>
<td> 14 </td>
<td> Maskable interrupts (one-hot signal) </td>
</tr>
<tr>
<td> nmi </td>
<td> Input </td>
<td> 1 </td>
<td> Non-maskable interrupt (asynchronous) </td>
</tr>
<tr>
<td> irq_acc </td>
<td> Output </td>
<td> 14 </td>
<td> Interrupt request accepted (one-hot signal) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
<tr>
<td> dbg_en </td>
<td> Input </td>
<td> 1 </td>
<td> Debug interface enable (asynchronous) <b><sup><font color="#FF0000">3</font></sup></b> </td>
</tr>
<tr>
<td> dbg_freeze </td>
<td> Output </td>
<td> 1 </td>
<td> Freeze peripherals </td>
</tr>
<tr>
<td> dbg_uart_txd </td>
<td> Output </td>
<td> 1 </td>
<td> Debug interface: UART TXD </td>
</tr>
<tr>
<td> dbg_uart_rxd </td>
<td> Input </td>
<td> 1 </td>
<td> Debug interface: UART RXD (asynchronous) </td>
</tr>
</table>
<br />
<b><sup><font color="#FF0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
<b><sup><font color="#FF0000">2</font></sup></b>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.<br />
<b><sup><font color="#FF0000">3</font></sup></b>: When disabled, the debug interface is hold into reset. As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br />
<br />
<a name="2.1.6 Instruction Cycles and Lengths"></a>
<h3>2.1.6 Instruction Cycles and Lengths</h3>
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br /><br />
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.<br />
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
Differences with the original MSP430 are highlighted in green (the original value being red).
<ul>
<li><b>Interrupt and Reset Cycles</b></li>
</ul>
<table border="1">
<tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
</table>
<ul>
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
</ul>
<table border="1">
<tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
</table>
<ul>
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
</ul>
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
<ul>
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
</ul>
<table border="1">
<tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
</table>
<a name="2.1.7 Serial Debug Interface"></a>
<h3>2.1.7 Serial Debug Interface</h3>
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
<a name="2.2 Peripherals"></a>
<h2>2.2 Peripherals</h2>
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
<a name="2.2.1 Basic Clock Module"></a>
<h3>2.2.1 Basic Clock Module</h3>
In order to make an FPGA implementation as simple as possible (ideally, a non-designer should be able to do it), clock gates are not used in the design and neither are clock muxes.
<br />
With these constrains, the Basic Clock Module is implemented as following:
<br /><br />
<img src="getimg.php?1249244393" alt="Clock structure diagram" title="Clock structure diagram" />
<br />
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.
<br /><br />
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
<br /><br />
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
<br /><br />
The following Verilog code would implement a counter clocked with SMCLK:
<br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
reg [7:0] test_cnt;
<br />
<br />always @ (posedge mclk or posedge puc_rst)
<br /> if (puc_rst) test_cnt <= 8'h00;
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
</code>
</td>
</tr>
</table>
<br /><br />
<b>Register Description</b>
<ul>
<li>DCOCTL: Not implemented</li>
<li>BCSCTL1:
<ul>
<li>BCSCTL1[7:6]: Unused</li>
<li>BCSCTL1[5:4]: DIVAx</li>
<li>BCSCTL1[4:0]: Unused</li>
</ul>
</li>
<li>BCSCTL2:
<ul>
<li>BCSCTL2[7:4]: Unused</li>
<li>BCSCTL2[3] : SELS</li>
<li>BCSCTL2[2:1]: DIVSx</li>
<li>BCSCTL2[0] : Unused</li>
</ul>
</li>
</ul>
<a name="2.2.2 Watchdog Timer"></a>
<h3>2.2.2 Watchdog Timer</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.
<a name="2.2.3 Digital I/O"></a>
<h3>2.2.3 Digital I/O</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
<br /><br />
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
parameter P1_EN = 1'b1; // Enable Port 1
<br />parameter P2_EN = 1'b1; // Enable Port 2
<br />parameter P3_EN = 1'b0; // Enable Port 3
<br />parameter P4_EN = 1'b0; // Enable Port 4
<br />parameter P5_EN = 1'b0; // Enable Port 5
<br />parameter P6_EN = 1'b0; // Enable Port 6
</code>
</td>
</tr>
</table>
<br />
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
gpio #(.P1_EN(1),
<br /> .P2_EN(1),
<br /> .P3_EN(1),
<br /> .P4_EN(0),
<br /> .P5_EN(0),
<br /> .P6_EN(0)) gpio_0 (
</code>
</td>
</tr>
</table>
<br />
The full pinout of the GPIO module is provided in the following table:
<br /><br />
<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
</table>
<a name="2.2.4 Timer A"></a>
<h3>2.2.4 Timer A</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
<br /><br />
The full pinout of the Timer A module is provided in the following table:
<br /><br />
<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
</table>
<br />
<b>Note</b>: for the same reason as with the Basic Clock Module, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain.
As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output.
If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.
<br /><br />
<a name="2.2.5 16x16 Hardware Multiplier"></a>
<h3>2.2.5 16x16 Hardware Multiplier</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
<br /><br />
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not.
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
// Include/Exclude Hardware Multiplier
<br />`define MULTIPLIER
</code>
</td>
</tr>
</table>
<br /><br />
<br /><br />
</body>
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