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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
<html>
<head>
<title>openMSP430 Core</title>
</head>
<body>
<h3>Table of content</h3>
<ul>
<li><a href="#1. Introduction">1. Introduction</a></li>
<li><a href="#2. Design"> 2. Design</a>
<ul>
<li><a href="#2.1 Core"> 2.1 Core</a>
<ul>
<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
<li><a href="#2.1.4 Pinout"> 2.1.4 Pinout</a></li>
<li><a href="#2.1.5 Instruction Cycles and Lengths">2.1.5 Instruction Cycles and Lengths</a></li>
<li><a href="#2.1.6 Serial Debug Interface"> 2.1.6 Serial Debug Interface</a></li>
</ul>
</li>
<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
<ul>
<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
<li><a href="#2.2.2 Watchdog Timer"> 2.2.2 Watchdog Timer</a></li>
<li><a href="#2.2.3 Digital I/O"> 2.2.3 Digital I/O</a></li>
<li><a href="#2.2.4 Timer A"> 2.2.4 Timer A</a></li>
</ul>
</li>
</ul>
</li>
</ul>
<a name="1. Introduction"></a>
<h1>1. Introduction</h1>
The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
<br /><br />
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
<br /><br />
This IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
<br /><br />
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
<br /><br />
<a name="2. Design"></a>
<h1>2. Design</h1>
<a name="2.1 Core"></a>
<h2>2.1 Core</h2>
<a name="2.1.1 Design structure"></a>
<h3>2.1.1 Design structure</h3>
The following diagram shows the openMSP430 design structure:
<br /><br />
<img src="getimg.php?1262105776" width="100%" alt="CPU Structure" title="CPU Structure" />
<br />
<ul>
<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
</ul>
<a name="2.1.2 Limitations"></a>
<h3>2.1.2 Limitations</h3>
The known core limitations are the following:
<br />
<ul>
<li>Instructions can't be executed from the data memory.</li>
<li>SCG0 is not implemented (turns off DCO).</li>
<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li>
</ul>
<a name="2.1.3 Configuration"></a>
<h3>2.1.3 Configuration</h3>
It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
Two parameters can be adjusted by the user in order to define the program and data memory sizes:
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
// Program Memory Size
<br />// 9 -> 1 kB
<br />// 10 -> 2 kB
<br />// 11 -> 4 kB
<br />// 12 -> 8 kB
<br />// 13 -> 16 kB
<br />// 14 -> 32 kB
<br />`define PMEM_AWIDTH 10
<br />
<br />// Data Memory Size
<br />// 6 -> 128 B
<br />// 7 -> 256 B
<br />// 8 -> 512 B
<br />// 9 -> 1 kB
<br />// 10 -> 2 kB
<br />// 11 -> 4 kB
<br />// 12 -> 8 kB
<br />// 13 -> 16 kB
<br />// 14 -> 32 kB
<br />`define DMEM_AWIDTH 6
</code>
</td>
</tr>
</table>
<br /><br />
<b>Note:</b> Program and data memories <b>SHOULD NOT</b> be both set to 32 kB
<br /><br /><br />
The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included.
<br /><br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
//----------------------------------------------------------------------------
<br />// REMOTE DEBUGGING INTERFACE CONFIGURATION
<br />//----------------------------------------------------------------------------
<br />
<br />// Include Debug interface
<br />`define DBG_EN
<br />
<br />// Debug interface selection
<br />// `define DBG_UART -> Enable UART (8N1) debug interface
<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
<br />//
<br />`define DBG_UART
<br />//`define DBG_JTAG
<br />
<br />// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
<br />// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
<br />// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
<br />// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
<br />// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
<br />//
<br />`define DBG_HWBRK_0
<br />`define DBG_HWBRK_1
<br />`define DBG_HWBRK_2
<br />`define DBG_HWBRK_3
</code>
</td>
</tr>
</table>
<br /><br />
<b>Note:</b> Since the hardware breakpoint units are relatively big, it is recommended to include as many as you plan to use. These units are particularly useful if your instruction memory is a ROM (i.e. when you can't use software breakpoints) or if you want to be able to stop the CPU whenever some particular data addresses are accessed.
<br /><br /><br />
All remaining defines located in this file are system constants and should not be edited.
<a name="2.1.4 Pinout"></a>
<h3>2.1.4 Pinout</h3>
The full pinout of the openMSP430 core is provided in the following table:
<br /><br />
<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
<tr>
<td> dco_clk </td>
<td> Input </td>
<td> 1 </td>
<td> Fast oscillator (fast clock), CPU clock </td>
</tr>
<tr>
<td> lfxt_clk </td>
<td> Input </td>
<td> 1 </td>
<td> Low frequency oscillator (typ. 32kHz) </td>
</tr>
<tr>
<td> mclk </td>
<td> Output </td>
<td> 1 </td>
<td> Main system clock </td>
</tr>
<tr>
<td> aclk_en </td>
<td> Output </td>
<td> 1 </td>
<td> ACLK enable </td>
</tr>
<tr>
<td> smclk_en </td>
<td> Output </td>
<td> 1 </td>
<td> SMCLK enable </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
<tr>
<td> puc </td>
<td> Output </td>
<td> 1 </td>
<td> Main system reset </td>
</tr>
<tr>
<td> reset_n </td>
<td> Input </td>
<td> 1 </td>
<td> Reset Pin (low active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
<tr>
<td> pmem_addr </td>
<td> Output </td>
<td> `PMEM_AWIDTH<sup>1</sup> </td>
<td> Program Memory address </td>
</tr>
<tr>
<td> pmem_cen </td>
<td> Output </td>
<td> 1 </td>
<td> Program Memory chip enable (low active) </td>
</tr>
<tr>
<td> pmem_din </td>
<td> Output </td>
<td> 16 </td>
<td> Program Memory data input (optional<sup>2</sup>) </td>
</tr>
<tr>
<td> pmem_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Program Memory data output </td>
</tr>
<tr>
<td> pmem_wen </td>
<td> Output </td>
<td> 2 </td>
<td> Program Memory write enable (low active) (optional<sup>2</sup>) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
<tr>
<td> dmem_addr </td>
<td> Output </td>
<td> `DMEM_AWIDTH<sup>1</sup> </td>
<td> Data Memory address </td>
</tr>
<tr>
<td> dmem_cen </td>
<td> Output </td>
<td> 1 </td>
<td> Data Memory chip enable (low active) </td>
</tr>
<tr>
<td> dmem_din </td>
<td> Output </td>
<td> 16 </td>
<td> Data Memory data input </td>
</tr>
<tr>
<td> dmem_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Data Memory data output </td>
</tr>
<tr>
<td> dmem_wen </td>
<td> Output </td>
<td> 2 </td>
<td> Data Memory write enable (low active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr>
<td> per_addr </td>
<td> Output </td>
<td> 8 </td>
<td> Peripheral address </td>
</tr>
<tr>
<td> per_din </td>
<td> Output </td>
<td> 16 </td>
<td> Peripheral data input </td>
</tr>
<tr>
<td> per_dout </td>
<td> Input </td>
<td> 16 </td>
<td> Peripheral data output </td>
</tr>
<tr>
<td> per_en </td>
<td> Output </td>
<td> 1 </td>
<td> Peripheral enable (high active) </td>
</tr>
<tr>
<td> per_wen </td>
<td> Output </td>
<td> 2 </td>
<td> Peripheral write enable (high active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr>
<td> irq </td>
<td> Input </td>
<td> 14 </td>
<td> Maskable interrupts (one-hot signal) </td>
</tr>
<tr>
<td> nmi </td>
<td> Input </td>
<td> 1 </td>
<td> Non-maskable interrupt (asynchronous) </td>
</tr>
<tr>
<td> irq_acc </td>
<td> Output </td>
<td> 14 </td>
<td> Interrupt request accepted (one-hot signal) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
<tr>
<td> dbg_freeze </td>
<td> Output </td>
<td> 1 </td>
<td> Freeze peripherals </td>
</tr>
<tr>
<td> dbg_uart_txd </td>
<td> Output </td>
<td> 1 </td>
<td> Debug interface: UART TXD </td>
</tr>
<tr>
<td> dbg_uart_rxd </td>
<td> Input </td>
<td> 1 </td>
<td> Debug interface: UART RXD </td>
</tr>
</table>
<br />
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
<sup>2</sup>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.
<br /><br />
<a name="2.1.5 Instruction Cycles and Lengths"></a>
<h3>2.1.5 Instruction Cycles and Lengths</h3>
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.
<br />In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
Differences with the original MSP430 are highlighted in green (the original value being red).
<ul>
<li><b>Interrupt and Reset Cycles</b></li>
</ul>
<table border="1">
<tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
</table>
<ul>
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
</ul>
<table border="1">
<tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
</table>
<ul>
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
</ul>
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
<ul>
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
</ul>
<table border="1">
<tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
</table>
<a name="2.1.6 Serial Debug Interface"></a>
<h3>2.1.6 Serial Debug Interface</h3>
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
<a name="2.2 Peripherals"></a>
<h2>2.2 Peripherals</h2>
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
<a name="2.2.1 Basic Clock Module"></a>
<h3>2.2.1 Basic Clock Module</h3>
In order to make an FPGA implementation as simple as possible (ideally, a non-designer should be able to do it), clock gates are not used in the design and neither are clock muxes.
<br />
With these constrains, the Basic Clock Module is implemented as following:
<br /><br />
<img src="getimg.php?1249244393" alt="Clock structure diagram" title="Clock structure diagram" />
<br />
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.
<br /><br />
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
<br /><br />
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
<br /><br />
The following Verilog code would implement a counter clocked with SMCLK:
<br />
<table border="0" cellspacing="4" cellpadding="0">
<tr>
<td width="35"></td>
<td bgcolor="#d0d0d0" width="3"></td>
<td width="15"></td>
<td>
<code>
reg [7:0] test_cnt;
<br />
<br />always @ (posedge mclk or posedge puc)
<br /> if (puc) test_cnt <= 8'h00;
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
</code>
</td>
</tr>
</table>
<br /><br />
<b>Register Description</b>
<ul>
<li>DCOCTL: Not implemented</li>
<li>BCSCTL1:
<ul>
<li>BCSCTL1[7:6]: Unused</li>
<li>BCSCTL1[5:4]: DIVAx</li>
<li>BCSCTL1[4:0]: Unused</li>
</ul>
</li>
<li>BCSCTL2:
<ul>
<li>BCSCTL2[7:4]: Unused</li>
<li>BCSCTL2[3] : SELS</li>
<li>BCSCTL2[2:1]: DIVSx</li>
<li>BCSCTL2[0] : Unused</li>
</ul>
</li>
</ul>
<a name="2.2.2 Watchdog Timer"></a>
<h3>2.2.2 Watchdog Timer</h3>
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 10) have been implemented.
<a name="2.2.3 Digital I/O"></a>
<h3>2.2.3 Digital I/O</h3>
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 9) have been implemented.
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The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
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<code>
parameter P1_EN = 1'b1; // Enable Port 1
<br />parameter P2_EN = 1'b1; // Enable Port 2
<br />parameter P3_EN = 1'b0; // Enable Port 3
<br />parameter P4_EN = 1'b0; // Enable Port 4
<br />parameter P5_EN = 1'b0; // Enable Port 5
<br />parameter P6_EN = 1'b0; // Enable Port 6
</code>
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They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
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<code>
gpio #(.P1_EN(1),
<br /> .P2_EN(1),
<br /> .P3_EN(1),
<br /> .P4_EN(0),
<br /> .P5_EN(0),
<br /> .P6_EN(0)) gpio_0 (
</code>
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<br />
The full pinout of the GPIO module is provided in the following table:
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<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
</table>
<a name="2.2.4 Timer A"></a>
<h3>2.2.4 Timer A</h3>
100% of the features advertised in the MSP430x1xx Family User's Guide (Chapter 11) have been implemented.
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The full pinout of the Timer A module is provided in the following table:
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<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
</table>
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<b>Note</b>: for the same reason as with the Basic Clock Module, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain.
As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output.
If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.
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