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<head>
<title>openMSP430 Integration and Connectivity</title>
</head>
<body>
<a name="TOC"></a>
<h3>Table of content</h3>
<ul>
<li><a href="#1. Overview"> 1. Overview</a></li>
<li><a href="#2. Clocks"> 2. Clocks</a></li>
<li><a href="#3. Resets"> 3. Resets</a></li>
<li><a href="#4. Program Memory"> 4. Program Memory</a></li>
<li><a href="#5. Data Memory"> 5. Data Memory</a></li>
<li><a href="#6. Peripherals"> 6. Peripherals</a></li>
<li><a href="#7. Interrupts"> 7. Interrupts</a></li>
<li><a href="#8. Serial Debug Interface">8. Serial Debug Interface</a></li>
</ul>
<a name="1. Overview"></a>
<h1>1. Overview</h1>
This chapter aims to give a comprehensive description of all openMSP430 core interfaces in order to facilitates its integration within an ASIC or FPGA.<br /><br />
The following diagram shows an overview of the openMSP430 core connectivity:<br /><br />
<img src="usercontent,img,1306268589" width="100%" alt="Core Integration - 24 May 2011" title="Core Integration - 24 May 2011" />
<br /><br />
The full pinout of the core is summarized in the following table.<br />
<br />
<table border="1">
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
<tr>
<td> <a href="#2. Clocks">cpu_en</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Enable CPU code execution (asynchronous) </td>
</tr>
<tr>
<td> <a href="#2. Clocks">dco_clk</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Fast oscillator (fast clock), CPU clock </td>
</tr>
<tr>
<td> <a href="#2. Clocks">lfxt_clk</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Low frequency oscillator (typ. 32kHz) </td>
</tr>
<tr>
<td> <a href="#2. Clocks">mclk</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Main system clock </td>
</tr>
<tr>
<td> <a href="#2. Clocks">aclk_en</a> </td>
<td> Output </td>
<td> 1 </td>
<td> ACLK enable </td>
</tr>
<tr>
<td> <a href="#2. Clocks">smclk_en</a> </td>
<td> Output </td>
<td> 1 </td>
<td> SMCLK enable </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
<tr>
<td> <a href="#3. Resets">puc_rst</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Main system reset </td>
</tr>
<tr>
<td> <a href="#3. Resets">reset_n</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Reset Pin (low active, asynchronous) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
<tr>
<td> <a href="#4. Program Memory">pmem_addr</a> </td>
<td> Output </td>
<td> `PMEM_AWIDTH<sup>1</sup> </td>
<td> Program Memory address </td>
</tr>
<tr>
<td> <a href="#4. Program Memory">pmem_cen</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Program Memory chip enable (low active) </td>
</tr>
<tr>
<td> <a href="#4. Program Memory">pmem_din</a> </td>
<td> Output </td>
<td> 16 </td>
<td> Program Memory data input </td>
</tr>
<tr>
<td> <a href="#4. Program Memory">pmem_dout</a> </td>
<td> Input </td>
<td> 16 </td>
<td> Program Memory data output </td>
</tr>
<tr>
<td> <a href="#4. Program Memory">pmem_wen</a> </td>
<td> Output </td>
<td> 2 </td>
<td> Program Memory write byte enable (low active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
<tr>
<td> <a href="#5. Data Memory">dmem_addr</a> </td>
<td> Output </td>
<td> `DMEM_AWIDTH<sup>1</sup> </td>
<td> Data Memory address </td>
</tr>
<tr>
<td> <a href="#5. Data Memory">dmem_cen</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Data Memory chip enable (low active) </td>
</tr>
<tr>
<td> <a href="#5. Data Memory">dmem_din</a> </td>
<td> Output </td>
<td> 16 </td>
<td> Data Memory data input </td>
</tr>
<tr>
<td> <a href="#5. Data Memory">dmem_dout</a> </td>
<td> Input </td>
<td> 16 </td>
<td> Data Memory data output </td>
</tr>
<tr>
<td> <a href="#5. Data Memory">dmem_wen</a> </td>
<td> Output </td>
<td> 2 </td>
<td> Data Memory write byte enable (low active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr>
<td> <a href="#6. Peripherals">per_addr</a> </td>
<td> Output </td>
<td> 14 </td>
<td> Peripheral address </td>
</tr>
<tr>
<td> <a href="#6. Peripherals">per_din</a> </td>
<td> Output </td>
<td> 16 </td>
<td> Peripheral data input </td>
</tr>
<tr>
<td> <a href="#6. Peripherals">per_dout</a> </td>
<td> Input </td>
<td> 16 </td>
<td> Peripheral data output </td>
</tr>
<tr>
<td> <a href="#6. Peripherals">per_en</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Peripheral enable (high active) </td>
</tr>
<tr>
<td> <a href="#6. Peripherals">per_we</a> </td>
<td> Output </td>
<td> 2 </td>
<td> Peripheral write byte enable (high active) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr>
<td> <a href="#7. Interrupts">irq</a> </td>
<td> Input </td>
<td> 14 </td>
<td> Maskable interrupts (one-hot signal) </td>
</tr>
<tr>
<td> <a href="#7. Interrupts">nmi</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Non-maskable interrupt (asynchronous) </td>
</tr>
<tr>
<td> <a href="#7. Interrupts">irq_acc</a> </td>
<td> Output </td>
<td> 14 </td>
<td> Interrupt request accepted (one-hot signal) </td>
</tr>
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
<tr>
<td> <a href="#8. Serial Debug Interface">dbg_en</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Debug interface enable (asynchronous) </td>
</tr>
<tr>
<td> <a href="#8. Serial Debug Interface">dbg_freeze</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Freeze peripherals </td>
</tr>
<tr>
<td> <a href="#8. Serial Debug Interface">dbg_uart_txd</a> </td>
<td> Output </td>
<td> 1 </td>
<td> Debug interface: UART TXD </td>
</tr>
<tr>
<td> <a href="#8. Serial Debug Interface">dbg_uart_rxd</a> </td>
<td> Input </td>
<td> 1 </td>
<td> Debug interface: UART RXD (asynchronous) </td>
</tr>
</table>
<br />
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
<br />
<a name="2. Clocks"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>2. Clocks</h1>
The different clocks in the design are managed by the Basic Clock Module:
<br /><br />
<img src="getimg.php?1246434498" width="75%" alt="Clock structure diagram" title="Clock structure diagram" />
<br />
<ul>
<li>
<b><font color="#0000b0">CPU_EN</font></b>: this input port provide a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1.
<br /><br />
</li>
<li>
<b><font color="#0000b0">DCO_CLK</font></b>: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.<br />
From a synthesis tool perspective (ISE, Quartus, Libero, Design Compiler...), this the only port where a clock needs to be declared.
<br /><br />
</li>
<li>
<b><font color="#0000b0">LFXT_CLK</font></b>: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise.
<br /><br />
</li>
<li>
<b><font color="#00b000">MCLK</font></b>: the main system clock drives the complete openMSP430 clock domain, including program/data memories and the peripheral interfaces.
<br /><br />
</li>
<li>
<b><font color="#00b000">ACLK_EN / SMCLK_EN</font></b>: these two clock enable signals can be used in order to emulate the original ACLK and SMCLK from the MSP430 specification.<br />
An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:<br /><br />
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
<br /><br />
</li>
</ul>
As an illustration, the following waveform shows the different clocks where the software running on the openMSP430 configures the BCSCTL1 and BCSCTL2 registers so that <i>ACLK_EN</i> and <i>SMCLK_EN</i> are respectively running at <i>LFXT_CLK/2</i> and <i>DCO_CLK/4</i>.<br /><br />
<img src="getimg.php?1263320613" width="100%" alt="Waveforms: Clocks - Jan 12. 2010" title="Waveforms: Clocks - Jan 12. 2010" />
<br /><br />
<a name="3. Resets"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>3. Resets</h1>
<ul>
<li><b><font color="#0000b0">RESET_N</font></b>: this input port is typically connected to a board push button and is generally combined with the system power-on-reset.
<br /><br />
</li>
<li>
<b><font color="#00b000">PUC_RST</font></b>: the Power-Up-Clear signal is asynchronously set with the reset pin (<i>RESET_N</i>), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the <i>MCLK</i> clock domain.
<br /><br />
</li>
</ul>
The following waveform illustrates this:<br /><br />
<img src="getimg.php?1263320655" width="100%" alt="Waveforms: Resets - Jan 12. 2010" title="Waveforms: Resets - Jan 12. 2010" />
<br /><br />
<a name="4. Program Memory"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>4. Program Memory</h1>
Depending on the project needs, the program memory can be either implemented as a ROM or RAM.<br />
<br />
If a ROM is selected then the <i>PMEM_DIN</i> and <i>PMEM_WEN</i> ports won't be connected. In that case, the software debug capabilities are limited because the serial debug interface can only use hardware breakpoints in order to stop the program execution. In addition, updating the software will require a reprogramming of the FPGA.<br />
<br />
If the program memory is a RAM, the developer gets full flexibility regarding software debugging. The serial debug interface can be used to update the program memory and software breakpoints can be used.<br />
<br /><br />
That said, the protocol between the openMSP430 and the program memory is quite standard. Signal description goes as following:
<ul>
<li><b><font color="#00b000">PMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">PMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br />
<b>Note:</b> in order to calculate the core logical address from the program memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x10000-PMEM_SIZE</i>
<br /><br />
</li>
<li>
<b><font color="#0000b0">PMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>PMEM_DOUT</i> is not updated if <i>PMEM_CEN</i>=1).
<br /><br />
</li>
<li>
<b><font color="#00b000">PMEM_WEN</font></b>: this signal selects which byte should be written during a valid access. PMEM_WEN[0] will activate a write on the lower byte, PMEM_WEN[1] a write on the upper byte. Note that these signals are LOW ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">PMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>PMEM_WEN</i> value.
<br /><br />
</li>
</ul>
The following waveform illustrates some read accesses of the program memory (write access are illustrated in the data memory section):<br /><br />
<img src="getimg.php?1263320706" width="100%" alt="Waveforms: Program memory - Jan " title="Waveforms: Program memory - Jan " />
<br /><br />
<a name="5. Data Memory"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>5. Data Memory</h1>
The data memory is always implemented as a RAM.<br />
<br />
The protocol between the openMSP430 and the data memory is the same as the one of the program memory. Therefore, the signal description is the same:
<ul>
<li><b><font color="#00b000">DMEM_CEN</font></b>: when this signal is active, the read/write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is LOW ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">DMEM_ADDR</font></b>: Memory address of the 16 bit word which is going to be accessed.<br />
<b>Note:</b> in order to calculate the core logical address from the data memory physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@+0x200</i>
<br /><br />
</li>
<li>
<b><font color="#0000b0">DMEM_DOUT</font></b>: the memory output word will be updated with every valid read/write access (i.e. <i>DMEM_DOUT</i> is not updated if <i>DMEM_CEN</i>=1).
<br /><br />
</li>
<li>
<b><font color="#00b000">DMEM_WEN</font></b>: this signal selects which byte should be written during a valid access. DMEM_WEN[0] will activate a write on the lower byte, DMEM_WEN[1] a write on the upper byte. Note that these signals are LOW ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">DMEM_DIN</font></b>: the memory input word will be written with the valid write access according to the <i>DMEM_WEN</i> value.
<br /><br />
</li>
</ul>
The following waveform illustrates some read/write access to the data memory:<br /><br />
<img src="getimg.php?1263320770" width="100%" alt="Waveforms: Data memory - Jan 12." title="Waveforms: Data memory - Jan 12." />
<br /><br />
<a name="6. Peripherals"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>6. Peripherals</h1>
The protocol between the openMSP430 core and its peripherals is the exactly same as the one with the data and program memories in regards to write access and differs slightly for read access.<br />
<br />
On the connectivity side, the specificity is that the read data bus of all peripherals should be ORed together before being connected to the core, as showed in the diagram of the <a href="#1. Overview">Overview</a> section.<br />
From the logical point of view, during a read access, each peripheral outputs the combinatorial value of its read mux and returns 0 if it doesn't contain the addressed register. On the waveforms, this translates by seeing the register value on <i>PER_DOUT</i> while <i>PER_EN</i> is valid and not one clock cycle afterwards as it is the case with the program and data memories.<br />
In any case, it is recommended to use the templates provided with the core in order to develop your own custom peripherals.<br />
The signal description therefore goes as following:
<ul>
<li><b><font color="#00b000">PER_EN</font></b>: when this signal is active, read access are executed during the current <i>MCLK</i> cycle while write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is HIGH ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">PER_ADDR</font></b>: peripheral register address of the 16 bit word which is currently accessed. It is to be noted that a 14 bit address will always be provided from the openMSP430 to the peripheral in order to accommodate the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB as opposed to 512B by default).<br />
<b>Note:</b> in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@</i>
<br /><br />
</li>
<li>
<b><font color="#0000b0">PER_DOUT</font></b>: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise.
<br /><br />
</li>
<li>
<b><font color="#00b000">PER_WE</font></b>: this signal selects which byte should be written during a valid access. PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on the upper byte. Note that these signals are HIGH ACTIVE.
<br /><br />
</li>
<li>
<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
<br /><br />
</li>
</ul>
The following waveform illustrates some read/write access to the peripheral registers:<br /><br />
<img src="getimg.php?1263320825" width="100%" alt="Waveforms: Peripherals - Jan 12." title="Waveforms: Peripherals - Jan 12." />
<br /><br />
<a name="7. Interrupts"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>7. Interrupts</h1>
As with the original MSP430, the interrupt priorities of the openMSP430 are fixed in hardware accordingly to the connectivity of the <i>NMI</i> and <i>IRQ</i> ports.<br />
If two interrupts are pending simultaneously, the higher priority interrupt will be serviced first.<br />
The following table summarize this:<br /><br />
<table border="1">
<tr>
<td align="center"><b> Interrupt Port </b></td>
<td align="center"><b> Vector address </b></td>
<td align="center"><b> Priority </b></td>
</tr>
<tr>
<td align="center">RESET_N</td>
<td align="center">0xFFFE</td>
<td align="center">15 (highest)</td>
</tr>
<tr>
<td align="center">NMI</td>
<td align="center">0xFFFC</td>
<td align="center">14</td>
</tr>
<tr>
<td align="center">IRQ[13]</td>
<td align="center">0xFFFA</td>
<td align="center">13</td>
</tr>
<tr>
<td align="center">IRQ[12]</td>
<td align="center">0xFFF8</td>
<td align="center">12</td>
</tr>
<tr>
<td align="center">IRQ[11]</td>
<td align="center">0xFFF6</td>
<td align="center">11</td>
</tr>
<tr>
<td align="center">IRQ[10]</td>
<td align="center">0xFFF4</td>
<td align="center">10</td>
</tr>
<tr>
<td align="center">IRQ[9]</td>
<td align="center">0xFFF2</td>
<td align="center">9</td>
</tr>
<tr>
<td align="center">IRQ[8]</td>
<td align="center">0xFFF0</td>
<td align="center">8</td>
</tr>
<tr>
<td align="center">IRQ[7]</td>
<td align="center">0xFFEE</td>
<td align="center">7</td>
</tr>
<tr>
<td align="center">IRQ[6]</td>
<td align="center">0xFFEC</td>
<td align="center">6</td>
</tr>
<tr>
<td align="center">IRQ[5]</td>
<td align="center">0xFFEA</td>
<td align="center">5</td>
</tr>
<tr>
<td align="center">IRQ[4]</td>
<td align="center">0xFFE8</td>
<td align="center">4</td>
</tr>
<tr>
<td align="center">IRQ[3]</td>
<td align="center">0xFFE6</td>
<td align="center">3</td>
</tr>
<tr>
<td align="center">IRQ[2]</td>
<td align="center">0xFFE4</td>
<td align="center">2</td>
</tr>
<tr>
<td align="center">IRQ[1]</td>
<td align="center">0xFFE2</td>
<td align="center">1</td>
</tr>
<tr>
<td align="center">IRQ[0]</td>
<td align="center">0xFFE0</td>
<td align="center">0 (lowest)</td>
</tr>
</table>
<br /><br />
The signal description goes as following:
<ul>
<li>
<b><font color="#0000b0">NMI</font></b>: The <b>N</b>on-<b>M</b>askable <b>I</b>nterrupt has higher priority than other IRQs and is masked by the NMIIE bit instead of GIE.<br />
It is internally synchronized to the <i>MCLK</i> domain and can therefore be connected to any asynchronous signal of the chip (which could for example be a pin of the FPGA). If unused, this signal should be connected to 0.
<br /><br />
</li>
<li>
<b><font color="#0000b0">IRQ</font></b>: The standard interrupts can be connected to any signal coming from the <i>MCLK</i> domain (typically a peripheral). Priorities can be chosen by selecting the proper bit of the <i>IRQ</i> bus as shown in the table above. Unused interrupts should be connected to 0.<br />
<b>Note</b>: <i>IRQ[10]</i> is internally connected to the Watchdog interrupt. If this bit is also used by an external peripheral, they will both share the same interrupt vector.
<br /><br />
</li>
<li>
<b><font color="#00b000">IRQ_ACC</font></b>: Whenever an interrupt request is serviced, some peripheral automatically clear their pending flag in hardware. In order to do so, the <i>IRQ_ACC</i> bus can be used by using the bit matching the corresponding <i>IRQ</i> bit. An example of this is shown in the implementation of the TACCR0 Timer A interrupt.
<br /><br />
</li>
</ul>
The following waveform illustrates a TAIV interrupt issued by the Timer-A, which is connected to <i>IRQ[8]</i> :<br /><br />
<img src="getimg.php?1263320861" width="100%" alt="Waveforms: Interrupts - Jan 12. " title="Waveforms: Interrupts - Jan 12. " />
<br /><br />
<a name="8. Serial Debug Interface"></a>
<div style="text-align: right"><a href="#TOC">Top</a></div>
<h1>8. Serial Debug Interface</h1>
The serial debug interface module provides a two-wires communication bus for remote debugging and an additional freeze signal which might be useful for some peripherals.<br />
<br />
<ul>
<li>
<b><font color="#0000b0">DBG_EN</font></b>: this signal allows the user to enable or disable the serial debug interface without interfering with the CPU execution. It is to be noted that when disabled (i.e. DBG_EN=0), the debug interface is held into reset.
<br /><br />
</li>
<li>
<b><font color="#00b000">DBG_FREEZE</font></b>: this signal will be set whenever the debug interface stops the CPU (and if the <i>FRZ_BRK_EN</i> field of the <a href="http://www.opencores.org/project,openmsp430,serial%20debug%20interface#2.2.2%20CPU_CTL">CPU_CTL</a> debug register is set). As its name implies, the purpose of <i>DBG_FREEZE</i> is to freeze a peripheral whenever the CPU is stopped by the software debugger.<br />
For example, it is used by the Watchdog timer in order to stop its free-running counter. This prevents the CPU from being reseted by the watchdog every times the user stops the CPU during a debugging session.
<br /><br />
</li>
<li>
<b><font color="#00b000">DBG_UART_TXD</font> / <font color="#0000b0">DBG_UART_RXD</font></b>: these signals are typically connected to an RS-232 transceiver and will allow a PC to communicate with the openMSP430 core.
<br /><br />
</li>
</ul>
The following waveform shows some communication traffic on the serial bus :<br /><br />
<img src="getimg.php?1263320887" width="100%" alt="Waveforms: SDI - Jan 12. 2010" title="Waveforms: SDI - Jan 12. 2010" />
<br /><br />
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