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<html><head><title>openMSP430 Core</title></head>
<body>
<h3>Table of content</h3>
<ul>
<li><a href="#1.%20Introduction"> 1. Introduction</a></li>
<li><a href="#2.%20Peripherals"> 2. Peripherals</a>
<ul>
<li><a href="#2.1_System_Peripherals"> 2.1 System Peripherals</a>
<ul>
<li><a href="#2.1.1%20Basic%20Clock%20Module"> 2.1.1 Basic Clock Module: FPGA</a></li>
<li><a href="#2.1.2_Basic_Clock_Module_ASIC"> 2.1.2 Basic Clock Module: ASIC</a></li>
<li><a href="#2.1.3_SFR"> 2.1.3 SFR</a><br></li>
<li><a href="#2.1.4%20Watchdog%20Timer"> 2.1.4 Watchdog Timer</a></li>
<li><a href="#2.1.5%2016x16%20Hardware%20Multiplier"> 2.1.5 16x16 Hardware Multiplier</a></li>
</ul>
</li>
<li><a href="#2.2_External_Peripherals"> 2.2 External Peripherals</a>
<ul>
<li><a href="#2.2.1%20Digital%20I/O"> 2.2.1 Digital I/O (FPGA ONLY)</a></li>
<li><a href="#2.2.2%20Timer%20A"> 2.2.2 Timer A (FPGA ONLY)</a></li>
</ul>
</li>
</ul>
</li>
</ul>
<a name="1. Introduction"></a>
<h1>1. Introduction</h1>
In addition to the CPU core itself, several peripherals are
also provided and can be easily connected to the core during
integration.
<br><br>
<a name="2. Peripherals"></a>
<h1>2. Peripherals</h1>
<a name="2.1_System_Peripherals"></a>
<h2>2.1 System Peripherals</h2>
In addition to the CPU core itself, several peripherals are also
provided and can be easily connected to the core during integration.
The followings are directly integrated within the core because of their
tight links with the CPU.<br>
It is to be noted that <span style="font-weight: bold;">ALL</span> system peripherals support both ASIC and FPGA versions.<br>
<a name="2.1.1 Basic Clock Module"></a>
<h3>2.1.1 Basic Clock Module: FPGA</h3>
<br>
In order to make an FPGA
implementation as simple as possible (ideally, a non-professional designer should be
able to do it), clock gates are not used in this design configuration and neither are
clock muxes.
<br>
With these constrains, the Basic Clock Module is implemented as following:
<br><br>
<img src="http://opencores.org/usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="80%">
<br>
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the
CPU state machines in an IDLE state while MCLK will still be running.
<br><br>
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
<br><br>
<img src="http://opencores.org/usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example">
<br><br>For example, the following Verilog code would implement a counter clocked with SMCLK:
<br>
<table border="0" cellpadding="0" cellspacing="4">
<tbody><tr>
<td width="35"><br>
</td>
<td bgcolor="#d0d0d0" width="3"><br>
</td>
<td width="15"><br>
</td>
<td>
<code>
reg [7:0] test_cnt;
<br>
<br>always @ (posedge mclk or posedge puc_rst)
<br> if (puc_rst) test_cnt <= 8'h00;
<br> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
</code>
</td>
</tr>
</tbody></table>
<br><br>
<b>Register Description (FPGA)</b>
<br><br>
<table border="1">
<tbody><tr align="center">
<td rowspan="2"><b>Register Name</b></td>
<td rowspan="2"><b>Address</b></td>
<td colspan="16"><b>Bit Field</b></td>
</tr>
<tr align="center">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr align="center">
<td>DCOCTL</td>
<td>0x0004</td>
<td colspan="8"><small><i>not implemented</i></small></td>
</tr>
<tr align="center">
<td>BCSTL1</td>
<td>0x0006</td>
<td colspan="2"><small><i>unused</i></small></td>
<td colspan="2"><b>DIVAx</b></td>
<td colspan="4"><small><i>unused</i></small></td>
</tr>
<tr align="center">
<td>BCSTL2</td>
<td>0x0008</td>
<td colspan="4"><small><i>unused</i></small></td>
<td colspan="1"><b>SELS</b></td>
<td colspan="2"><b>DIVSx</b></td>
<td colspan="1"><small><i>unused</i></small></td>
</tr>
</tbody>
</table>
<ul>
<li>BCSCTL1.<b>DIVAx</b> : ACLK_EN divider (1/2/4/8)</li>
<li>BCSCTL2.<b>SELS</b>  : SMCLK_EN clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
<li>BCSCTL2.<b>DIVSx</b> : SMCLK_EN divider (1/2/4/8)</li>
</ul>
<a name="2.1.2_Basic_Clock_Module_ASIC"></a>
<h3>2.1.2 Basic Clock Module: ASIC</h3>
<br>
When targeting an ASIC, up to all clock management
options available in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 4) can be included:<br><br>
<img src="http://opencores.org/usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="80%"><br>
Additional info can be found in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
section.<br>
<br>
<b>Register Description (ASIC)</b>
<br><br>
<table border="1">
<tbody><tr align="center">
<td rowspan="2"><b>Register Name</b></td>
<td rowspan="2"><b>Address</b></td>
<td colspan="16"><b>Bit Field</b></td>
</tr>
<tr align="center">
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td>
</tr>
<tr align="center">
<td>DCOCTL</td>
<td>0x0004</td>
<td colspan="8"><small><i>not implemented</i></small></td>
</tr>
<tr align="center">
<td>BCSTL1</td>
<td>0x0006</td>
<td colspan="2"><small><i>unused</i></small></td>
<td colspan="2"><b>DIVAx</b></td>
<td colspan="1"><b><small>DMA_SCG1</small></b></td>
<td colspan="1"><b><small>DMA_SCG0</small></b></td>
<td colspan="1"><b><small>DMA_OSCOFF</small></b></td>
<td colspan="1"><b><small>DMA_CPUOFF</small></b></td>
</tr>
<tr align="center">
<td>BCSTL2</td>
<td>0x0008</td>
<td colspan="1"><b>SELMx</b></td>
<td colspan="1"><small><i>unused</i></small></td>
<td colspan="2"><b>DIVMx</b></td>
<td colspan="1"><b>SELS</b></td>
<td colspan="2"><b>DIVSx</b></td>
<td colspan="1"><small><i>unused</i></small></td>
</tr>
</tbody>
</table>
<ul>
<li>BCSCTL1.<b>DIVAx</b>     : ACLK clock divider (1/2/4/8)</li>
<li>BCSCTL1.<b>DMA_SCG1</b>   : Restore SMCLK with DMA wakeup</li>
<li>BCSCTL1.<b>DMA_SCG0</b>   : Restore DCO oscillator with DMA wakeup</li>
<li>BCSCTL1.<b>DMA_OSCOFF</b> : Restore LFXT oscillator with DMA wakeup</li>
<li>BCSCTL1.<b>DMA_CPUOFF</b> : Restore MCLK with DMA wakeup</li>
<li>BCSCTL2.<b>SELMx</b>     : MCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
<li>BCSCTL2.<b>DIVMx</b>     : MCLK clock divider (1/2/4/8)</li>
<li>BCSCTL2.<b>SELS</b>      : SMCLK clock selection (0:DCO_CLK / 1:LFXT_CLK)</li>
<li>BCSCTL2.<b>DIVSx</b>     : SMCLK clock divider (1/2/4/8)</li>
</ul>
<a name="2.1.3_SFR"></a>
<h3>2.1.3 SFR</h3>
Following the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a>, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:<br>
<br>
<table border="1">
<tbody><tr align="center">
<td rowspan="2"><b><small>Register Name</small></b></td>
<td rowspan="2"><b><small>Address</small></b></td>
<td colspan="8" rowspan="1" style="vertical-align: top;"><small style="font-weight: bold;">Bit Fields</small><br>
</td>
</tr>
<tr align="center">
<td style="vertical-align: top;"><small>7<br>
</small></td>
<td style="vertical-align: top;"><small>6<br>
</small></td>
<td style="vertical-align: top;"><small>5<br>
</small></td>
<td style="vertical-align: top;"><small>4<br>
</small></td>
<td style="vertical-align: top;"><small>3<br>
</small></td>
<td style="vertical-align: top;"><small>2<br>
</small></td>
<td style="vertical-align: top;"><small>1<br>
</small></td>
<td style="vertical-align: top;"><small>0<br>
</small></td>
</tr>
<tr align="center">
<td>IE1<br>
</td>
<td><small>0x0000</small></td>
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><small> Reserved <br>
</small></td>
<td style="vertical-align: top;">NMIIE <b><sup><font color="#ff0000">1</font></sup></b></td>
<td colspan="3" rowspan="1" style="vertical-align: top;"><small> Reserved </small>
</td>
<td style="vertical-align: top;">WDTIE <b><sup><font color="#ff0000">2</font></sup></b></td>
</tr>
<tr align="center">
<td>IFG1<br>
</td>
<td><small>0x0002</small></td>
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small><br>
</td>
<td style="vertical-align: top;">NMIIFG <b><sup><font color="#ff0000">1</font></sup></b></td>
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small></td>
<td style="vertical-align: top;">WDTIFG <b><sup><font color="#ff0000">2</font></sup></b></td>
</tr>
</tbody>
</table>
<br>
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
<br>
In addition, three 16-bit read-only registers have been added in order
to let the software know with which version of the openMSP430 it is
running:<br>
<br>
<table border="1">
<tbody><tr align="center">
<td rowspan="2"><b><small>Register Name</small></b></td>
<td rowspan="2"><b><small>Address</small></b></td>
<td colspan="16"><b><small>Bit Field</small></b></td>
</tr>
<tr align="center">
<td><small>15</small></td><td><small>14</small></td>
<td><small>13</small></td><td><small>12</small></td>
<td><small>11</small></td><td><small>10</small></td>
<td><small> 9</small></td><td><small> 8</small></td>
<td><small> 7</small></td><td><small> 6</small></td>
<td><small> 5</small></td><td><small> 4</small></td>
<td><small> 3</small></td><td><small> 2</small></td>
<td><small> 1</small></td><td><small> 0</small></td>
</tr>
<tr align="center">
<td><small>CPU_ID_LO</small></td>
<td><small>0x0004</small></td>
<td colspan="7"><font size="-5">PER_SPACE</font></td>
<td colspan="5"><font size="-5">USER_VERSION</font></td>
<td colspan="1"><font size="-5">ASIC</font></td>
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
</tr>
<tr align="center">
<td><small>CPU_ID_HI</small></td>
<td><small>0x0006</small></td>
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
<td colspan="1"><font size="-5">MPY</font></td>
</tr><tr>
<td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
<td style="vertical-align: top; text-align: center;"><small>0x0008</small></td>
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
</tr>
</tbody>
</table>
<br>
<table border="0">
<tbody><tr>
<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
<td>: Current CPU version<br>
</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>ASIC</b></li></td>
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
<td>: Reflects the value defined in the <b style="font-style: italic;">openMSP430_defines.v</b> file.</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>MPY</b></li></td>
<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
<td>: Current oMSP instance number (for multicore systems)</td>
</tr>
<tr>
<td> </td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
<td>: Total number of oMSP instances-1 (for multicore systems)</td>
</tr>
</tbody>
</table>
<br>
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span>, <span style="font-style: italic;">CPU_ID_HI</span> and <span style="font-style: italic;">CPU_NR</span> are identical to the Serial Debug Interface register counterparts.<br>
<a name="2.1.4 Watchdog Timer"></a>
<h3>2.1.4 Watchdog Timer</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.<br>
<br>
The following parameter in the <i>openMSP430_defines.v</i> file controls if the watchdog timer should be included or not:<br>
<br>
<table border="0" cellpadding="0" cellspacing="4">
<tbody><tr>
<td width="35"><br>
</td>
<td bgcolor="#d0d0d0" width="3"><br>
</td>
<td width="15"><br>
</td>
<td>
<code>//-------------------------------------------------------<br>
// Include/Exclude Watchdog timer<br>
//-------------------------------------------------------<br>
// When excluded, the following functionality will be<br>
// lost:<br>
// - Watchog (both interval and watchdog modes)<br>
// - NMI interrupt edge selection<br>
// - Possibility to generate a software PUC reset<br>
//-------------------------------------------------------<br>
`define WATCHDOG</code></td></tr></tbody>
</table>
<br>
<a name="2.1.5 16x16 Hardware Multiplier"></a>
<h3>2.1.5 16x16 Hardware Multiplier</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
<br><br>
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not:<br><br>
<table border="0" cellpadding="0" cellspacing="4">
<tbody><tr>
<td width="35"><br>
</td>
<td bgcolor="#d0d0d0" width="3"><br>
</td>
<td width="15"><br>
</td>
<td>
<code>
// Include/Exclude Hardware Multiplier
<br>`define MULTIPLIER
</code>
</td>
</tr>
</tbody></table>
<a name="2.2_External_Peripherals"></a>
<h2>2.2 External Peripherals</h2>
The external peripherals labeld with the "FPGA ONLY" tag do not contain
any clock gate nor clock muxes and are clocked with MCLK only. This
mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.<br>
<br>
<a name="2.2.1 Digital I/O"></a>
<h3>2.2.1 Digital I/O (FPGA ONLY)<br>
</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
<br>
<br>
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
<br>
<br>
<table border="0" cellpadding="0" cellspacing="4">
<tbody><tr>
<td width="35"><br>
</td>
<td bgcolor="#d0d0d0" width="3"><br>
</td>
<td width="15"><br>
</td>
<td>
<code>
parameter P1_EN = 1'b1; // Enable Port 1
<br>parameter P2_EN = 1'b1; // Enable Port 2
<br>parameter P3_EN = 1'b0; // Enable Port 3
<br>parameter P4_EN = 1'b0; // Enable Port 4
<br>parameter P5_EN = 1'b0; // Enable Port 5
<br>parameter P6_EN = 1'b0; // Enable Port 6
</code>
</td>
</tr>
</tbody>
</table>
<br>
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
<br>
<br>
<table border="0" cellpadding="0" cellspacing="4">
<tbody><tr>
<td width="35"><br>
</td>
<td bgcolor="#d0d0d0" width="3"><br>
</td>
<td width="15"><br>
</td>
<td>
<code>
gpio #(.P1_EN(1),
<br> .P2_EN(1),
<br> .P3_EN(1),
<br> .P4_EN(0),
<br> .P5_EN(0),
<br> .P6_EN(0)) gpio_0 (
</code>
</td>
</tr>
</tbody>
</table>
<br>
The full pinout of the GPIO module is provided in the following table:
<br>
<br>
<table border="1">
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 1</i></b> </td></tr>
<tr> <td> p1_din </td> <td> Input </td> <td> 8 </td> <td> Port 1 data input </td> </tr>
<tr> <td> p1_dout </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output </td> </tr>
<tr> <td> p1_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 1 data output enable </td> </tr>
<tr> <td> p1_sel </td> <td> Output </td> <td> 8 </td> <td> Port 1 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 2</i></b> </td></tr>
<tr> <td> p2_din </td> <td> Input </td> <td> 8 </td> <td> Port 2 data input </td> </tr>
<tr> <td> p2_dout </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output </td> </tr>
<tr> <td> p2_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 2 data output enable </td> </tr>
<tr> <td> p2_sel </td> <td> Output </td> <td> 8 </td> <td> Port 2 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 3</i></b> </td></tr>
<tr> <td> p3_din </td> <td> Input </td> <td> 8 </td> <td> Port 3 data input </td> </tr>
<tr> <td> p3_dout </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output </td> </tr>
<tr> <td> p3_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 3 data output enable </td> </tr>
<tr> <td> p3_sel </td> <td> Output </td> <td> 8 </td> <td> Port 3 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 4</i></b> </td></tr>
<tr> <td> p4_din </td> <td> Input </td> <td> 8 </td> <td> Port 4 data input </td> </tr>
<tr> <td> p4_dout </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output </td> </tr>
<tr> <td> p4_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 4 data output enable </td> </tr>
<tr> <td> p4_sel </td> <td> Output </td> <td> 8 </td> <td> Port 4 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 5</i></b> </td></tr>
<tr> <td> p5_din </td> <td> Input </td> <td> 8 </td> <td> Port 5 data input </td> </tr>
<tr> <td> p5_dout </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output </td> </tr>
<tr> <td> p5_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 5 data output enable </td> </tr>
<tr> <td> p5_sel </td> <td> Output </td> <td> 8 </td> <td> Port 5 function select </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
</tbody>
</table>
<a name="2.2.2 Timer A"></a>
<h3>2.2.2 Timer A (FPGA ONLY)</h3>
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
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The full pinout of the Timer A module is provided in the following table:
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<table border="1">
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr>
<tr> <td> irq_ta1 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TAIV, TACCR1, TACCR2 </td> </tr>
<tr> <td> irq_ta0_acc </td> <td> Input </td> <td> 1 </td> <td> Interrupt request TACCR0 accepted </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
<tr> <td> per_addr </td> <td> Input </td> <td> 8 </td> <td> Peripheral address </td> </tr>
<tr> <td> per_din </td> <td> Input </td> <td> 16 </td> <td> Peripheral data input </td> </tr>
<tr> <td> per_dout </td> <td> Output </td> <td> 16 </td> <td> Peripheral data output </td> </tr>
<tr> <td> per_en </td> <td> Input </td> <td> 1 </td> <td> Peripheral enable (high active) </td> </tr>
<tr> <td> per_wen </td> <td> Input </td> <td> 2 </td> <td> Peripheral write enable (high active) </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 0</i></b> </td></tr>
<tr> <td> ta_cci0a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input A </td> </tr>
<tr> <td> ta_cci0b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 0 input B </td> </tr>
<tr> <td> ta_out0 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 </td> </tr>
<tr> <td> ta_out0_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 0 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 1</i></b> </td></tr>
<tr> <td> ta_cci1a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input A </td> </tr>
<tr> <td> ta_cci1b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 1 input B </td> </tr>
<tr> <td> ta_out1 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 </td> </tr>
<tr> <td> ta_out1_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 1 enable </td> </tr>
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
</tbody>
</table>
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<b>Note</b>: for the same reason as with the Basic Clock Module FPGA version, the
two additional clock inputs (TACLK and INCLK) are internally
synchronized with the MCLK domain.
As a consequence, TACLK and INCLK should be at least 2 times slowlier
than MCLK, and if these clock are used toghether with the Timer A
output unit, some jitter might be observed on the generated output.
If this jitter is critical for the application, ACLK and INCLK should
idealy be derivated from DCO_CLK.
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