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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src/] [spacewar.v] - Rev 211

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/*===========================================================================*/
/*                                 DIGITAL I/O                               */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface.                                           */
/*===========================================================================*/
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge oscclk);
      stimulus_done = 0;
 
      repeat(50) @(posedge mclk);
 
      // Send uart synchronization frame
      dbg_uart_sync;
 
      // Let the CPU run
      dbg_uart_wr(CPU_CTL,  16'h0002);
 
      stimulus_done = 1;
   end
 
 

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