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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_constraints.post.sdc] - Rev 190
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# Design Constraintscreate_clock -name oscclk -period 20.0 -waveform [list 0.0 10.0] oscclkcreate_clock -name dco_clk -period 62.5 -waveform [list 0.0 31.25] pll_0:GLAset_false_path -from {pbrst_n}set_false_path -from {porst_n}
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