URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.map.smsg] - Rev 221
Compare with Previous | Blame | View Log
Info (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scopeInfo (10281): Verilog HDL Declaration information at DE0_NANO_SOC_QSYS_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scopeWarning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2120): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2122): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(2278): conditional expression evaluates to a constantWarning (10037): Verilog HDL or VHDL warning at DE0_NANO_SOC_QSYS_nios2_qsys.v(3102): conditional expression evaluates to a constant