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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [DE0_NANO_SOC_QSYS.cmp] - Rev 221
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component DE0_NANO_SOC_QSYS is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
adc_ltc2308_conduit_end_CONVST : out std_logic; -- CONVST
adc_ltc2308_conduit_end_SCK : out std_logic; -- SCK
adc_ltc2308_conduit_end_SDI : out std_logic; -- SDI
adc_ltc2308_conduit_end_SDO : in std_logic := 'X'; -- SDO
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
pll_sys_locked_export : out std_logic; -- export
pll_sys_outclk2_clk : out std_logic -- clk
);
end component DE0_NANO_SOC_QSYS;