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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [software/] [DE0_NANO_SOC_ADC_bsp/] [system.h] - Rev 221
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/* * system.h - SOPC Builder system and BSP software package information * * Machine generated for CPU 'nios2_qsys' in SOPC Builder design 'DE0_NANO_SOC_QSYS' * SOPC Builder design path: ../../DE0_NANO_SOC_QSYS.sopcinfo * * Generated: Thu Dec 18 16:09:20 CST 2014 */ /* * DO NOT MODIFY THIS FILE * * Changing this file will have subtle consequences * which will almost certainly lead to a nonfunctioning * system. If you do modify this file, be aware that your * changes will be overwritten and lost when this file * is generated again. * * DO NOT MODIFY THIS FILE */ /* * License Agreement * * Copyright (c) 2008 * Altera Corporation, San Jose, California, USA. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * This agreement shall be governed in all respects by the laws of the State * of California and by the laws of the United States of America. */ #ifndef __SYSTEM_H_ #define __SYSTEM_H_ /* Include definitions from linker script generator */ #include "linker.h" /* * CPU configuration * */ #define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" #define ALT_CPU_BIG_ENDIAN 0 #define ALT_CPU_BREAK_ADDR 0x00080820 #define ALT_CPU_CPU_FREQ 100000000u #define ALT_CPU_CPU_ID_SIZE 1 #define ALT_CPU_CPU_ID_VALUE 0x00000000 #define ALT_CPU_CPU_IMPLEMENTATION "fast" #define ALT_CPU_DATA_ADDR_WIDTH 0x14 #define ALT_CPU_DCACHE_LINE_SIZE 32 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 #define ALT_CPU_DCACHE_SIZE 2048 #define ALT_CPU_EXCEPTION_ADDR 0x00040020 #define ALT_CPU_FLUSHDA_SUPPORTED #define ALT_CPU_FREQ 100000000 #define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 #define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 #define ALT_CPU_HARDWARE_MULX_PRESENT 0 #define ALT_CPU_HAS_DEBUG_CORE 1 #define ALT_CPU_HAS_DEBUG_STUB #define ALT_CPU_HAS_JMPI_INSTRUCTION #define ALT_CPU_ICACHE_LINE_SIZE 32 #define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 #define ALT_CPU_ICACHE_SIZE 4096 #define ALT_CPU_INITDA_SUPPORTED #define ALT_CPU_INST_ADDR_WIDTH 0x14 #define ALT_CPU_NAME "nios2_qsys" #define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 #define ALT_CPU_RESET_ADDR 0x00040000 /* * CPU configuration (with legacy prefix - don't use these anymore) * */ #define NIOS2_BIG_ENDIAN 0 #define NIOS2_BREAK_ADDR 0x00080820 #define NIOS2_CPU_FREQ 100000000u #define NIOS2_CPU_ID_SIZE 1 #define NIOS2_CPU_ID_VALUE 0x00000000 #define NIOS2_CPU_IMPLEMENTATION "fast" #define NIOS2_DATA_ADDR_WIDTH 0x14 #define NIOS2_DCACHE_LINE_SIZE 32 #define NIOS2_DCACHE_LINE_SIZE_LOG2 5 #define NIOS2_DCACHE_SIZE 2048 #define NIOS2_EXCEPTION_ADDR 0x00040020 #define NIOS2_FLUSHDA_SUPPORTED #define NIOS2_HARDWARE_DIVIDE_PRESENT 0 #define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 #define NIOS2_HARDWARE_MULX_PRESENT 0 #define NIOS2_HAS_DEBUG_CORE 1 #define NIOS2_HAS_DEBUG_STUB #define NIOS2_HAS_JMPI_INSTRUCTION #define NIOS2_ICACHE_LINE_SIZE 32 #define NIOS2_ICACHE_LINE_SIZE_LOG2 5 #define NIOS2_ICACHE_SIZE 4096 #define NIOS2_INITDA_SUPPORTED #define NIOS2_INST_ADDR_WIDTH 0x14 #define NIOS2_NUM_OF_SHADOW_REG_SETS 0 #define NIOS2_RESET_ADDR 0x00040000 /* * Define for each module class mastered by the CPU * */ #define __ADC_LTC2308 #define __ALTERA_AVALON_JTAG_UART #define __ALTERA_AVALON_ONCHIP_MEMORY2 #define __ALTERA_AVALON_PIO #define __ALTERA_AVALON_SYSID_QSYS #define __ALTERA_NIOS2_QSYS /* * System configuration * */ #define ALT_DEVICE_FAMILY "Cyclone V" #define ALT_ENHANCED_INTERRUPT_API_PRESENT #define ALT_IRQ_BASE NULL #define ALT_LOG_PORT "/dev/null" #define ALT_LOG_PORT_BASE 0x0 #define ALT_LOG_PORT_DEV null #define ALT_LOG_PORT_TYPE "" #define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_STDERR "/dev/jtag_uart" #define ALT_STDERR_BASE 0x81000 #define ALT_STDERR_DEV jtag_uart #define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_PRESENT #define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN "/dev/jtag_uart" #define ALT_STDIN_BASE 0x81000 #define ALT_STDIN_DEV jtag_uart #define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_PRESENT #define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDOUT_BASE 0x81000 #define ALT_STDOUT_DEV jtag_uart #define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_PRESENT #define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" #define ALT_SYSTEM_NAME "DE0_NANO_SOC_QSYS" /* * adc_ltc2308 configuration * */ #define ADC_LTC2308_BASE 0x81010 #define ADC_LTC2308_IRQ -1 #define ADC_LTC2308_IRQ_INTERRUPT_CONTROLLER_ID -1 #define ADC_LTC2308_NAME "/dev/adc_ltc2308" #define ADC_LTC2308_SPAN 8 #define ADC_LTC2308_TYPE "adc_ltc2308" #define ALT_MODULE_CLASS_adc_ltc2308 adc_ltc2308 /* * hal configuration * */ #define ALT_MAX_FD 32 #define ALT_SYS_CLK none #define ALT_TIMESTAMP_CLK none /* * jtag_uart configuration * */ #define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart #define JTAG_UART_BASE 0x81000 #define JTAG_UART_IRQ 0 #define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_NAME "/dev/jtag_uart" #define JTAG_UART_READ_DEPTH 64 #define JTAG_UART_READ_THRESHOLD 8 #define JTAG_UART_SPAN 8 #define JTAG_UART_TYPE "altera_avalon_jtag_uart" #define JTAG_UART_WRITE_DEPTH 64 #define JTAG_UART_WRITE_THRESHOLD 8 /* * onchip_memory2 configuration * */ #define ALT_MODULE_CLASS_onchip_memory2 altera_avalon_onchip_memory2 #define ONCHIP_MEMORY2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 #define ONCHIP_MEMORY2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 #define ONCHIP_MEMORY2_BASE 0x40000 #define ONCHIP_MEMORY2_CONTENTS_INFO "" #define ONCHIP_MEMORY2_DUAL_PORT 0 #define ONCHIP_MEMORY2_GUI_RAM_BLOCK_TYPE "AUTO" #define ONCHIP_MEMORY2_INIT_CONTENTS_FILE "DE0_NANO_SOC_QSYS_onchip_memory2" #define ONCHIP_MEMORY2_INIT_MEM_CONTENT 1 #define ONCHIP_MEMORY2_INSTANCE_ID "NONE" #define ONCHIP_MEMORY2_IRQ -1 #define ONCHIP_MEMORY2_IRQ_INTERRUPT_CONTROLLER_ID -1 #define ONCHIP_MEMORY2_NAME "/dev/onchip_memory2" #define ONCHIP_MEMORY2_NON_DEFAULT_INIT_FILE_ENABLED 0 #define ONCHIP_MEMORY2_RAM_BLOCK_TYPE "AUTO" #define ONCHIP_MEMORY2_READ_DURING_WRITE_MODE "DONT_CARE" #define ONCHIP_MEMORY2_SINGLE_CLOCK_OP 0 #define ONCHIP_MEMORY2_SIZE_MULTIPLE 1 #define ONCHIP_MEMORY2_SIZE_VALUE 160000 #define ONCHIP_MEMORY2_SPAN 160000 #define ONCHIP_MEMORY2_TYPE "altera_avalon_onchip_memory2" #define ONCHIP_MEMORY2_WRITABLE 1 /* * sw configuration * */ #define ALT_MODULE_CLASS_sw altera_avalon_pio #define SW_BASE 0x0 #define SW_BIT_CLEARING_EDGE_REGISTER 0 #define SW_BIT_MODIFYING_OUTPUT_REGISTER 0 #define SW_CAPTURE 1 #define SW_DATA_WIDTH 10 #define SW_DO_TEST_BENCH_WIRING 0 #define SW_DRIVEN_SIM_VALUE 0 #define SW_EDGE_TYPE "ANY" #define SW_FREQ 100000000 #define SW_HAS_IN 1 #define SW_HAS_OUT 0 #define SW_HAS_TRI 0 #define SW_IRQ 1 #define SW_IRQ_INTERRUPT_CONTROLLER_ID 0 #define SW_IRQ_TYPE "EDGE" #define SW_NAME "/dev/sw" #define SW_RESET_VALUE 0 #define SW_SPAN 16 #define SW_TYPE "altera_avalon_pio" /* * sysid_qsys configuration * */ #define ALT_MODULE_CLASS_sysid_qsys altera_avalon_sysid_qsys #define SYSID_QSYS_BASE 0x81008 #define SYSID_QSYS_ID 0 #define SYSID_QSYS_IRQ -1 #define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SYSID_QSYS_NAME "/dev/sysid_qsys" #define SYSID_QSYS_SPAN 8 #define SYSID_QSYS_TIMESTAMP 1418889131 #define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys" #endif /* __SYSTEM_H_ */