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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.log] - Rev 157
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Welcome to Xilinx CORE Generator.Help system initialized.The IP Catalog has been reloaded.Wrote CGP file for project 'coregen'.Customize and GenerateINFO:sim:172 - Generating IP...Applying current project options...Finished applying current project options.Resolving generics for 'ram_16x512'...Applying external generics to 'ram_16x512'...Delivering associated files for 'ram_16x512'...WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name forVHDL synthesisDelivering EJava files for 'ram_16x512'...Generating implementation netlist for 'ram_16x512'...INFO:sim - Pre-processing HDL files for 'ram_16x512'...Running synthesis for 'ram_16x512'Running ngcbuild...Writing VHO instantiation template for 'ram_16x512'...Writing VHDL instantiation wrapper for 'ram_16x512'...Writing VHDL behavioral simulation model for 'ram_16x512'...WARNING:sim - No files were found for the view xilinx_documentationGenerating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol.Generating metadata file...Generating ISE project file for 'ram_16x512'...Generating ISE project...XCO file found: ram_16x512.xcoXMDF file found: ram_16x512_xmdf.tclAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.asy -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc -view all -origin_type createdChecking file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc" for project device match ...File"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc" device information matches project device.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.vhd -view all -origin_type createdINFO:HDLCompiler:1061 - Parsing VHDL file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.vho -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512_synth.vhd -view all -origin_type createdINFO:HDLCompiler:1061 - Parsing VHDL file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512_synth.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Duplicate Design Unit 'ram_16x512' found in library 'work'WARNING:ProjectMgmt -"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.vhd" line 43 (active)WARNING:ProjectMgmt -"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512_synth.vhd" line 64INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.Top level has been set to "/ram_16x512"Generating README file...Generating FLIST file...INFO:sim:948 - Finished FLIST file generation.Launching README viewer...Moving files to output directory...Finished moving files to output directorySaved CGP file for project 'coregen'.Saved CGP file for project 'coregen'.Regenerate (Under Current Project Settings)INFO:sim:172 - Generating IP...Applying current project options...Finished applying current project options.Resolving generics for 'ram_16x512'...WARNING:sim - A core named 'ram_16x512' already exists in the project. Outputproducts for this core may be overwritten.Applying external generics to 'ram_16x512'...Delivering associated files for 'ram_16x512'...WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name forVerilog synthesisDelivering EJava files for 'ram_16x512'...Generating implementation netlist for 'ram_16x512'...INFO:sim - Pre-processing HDL files for 'ram_16x512'...Running synthesis for 'ram_16x512'Running ngcbuild...Writing VEO instantiation template for 'ram_16x512'...Writing Verilog instantiation wrapper for 'ram_16x512'...Writing Verilog behavioral simulation model for 'ram_16x512'...WARNING:sim - No files were found for the view xilinx_documentationGenerating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol.Generating metadata file...Regenerating ISE project file for 'ram_16x512'...Generating ISE project...XCO file found: ram_16x512.xcoXMDF file found: ram_16x512_xmdf.tclAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.asy -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc -view all -origin_type createdChecking file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc" for project device match ...File"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.ngc" device information matches project device.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512.veo -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512_synth.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x512_synth.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.Top level has been set to "/ram_16x512"Generating README file...Generating FLIST file...INFO:sim:948 - Finished FLIST file generation.Moving files to output directory...Finished moving files to output directorySaved CGP file for project 'coregen'.Customize and GenerateINFO:sim:172 - Generating IP...Applying current project options...Finished applying current project options.Resolving generics for 'ram_16x2k'...Applying external generics to 'ram_16x2k'...Delivering associated files for 'ram_16x2k'...WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name forVerilog synthesisDelivering EJava files for 'ram_16x2k'...Generating implementation netlist for 'ram_16x2k'...INFO:sim - Pre-processing HDL files for 'ram_16x2k'...Running synthesis for 'ram_16x2k'Running ngcbuild...Writing VEO instantiation template for 'ram_16x2k'...Writing Verilog instantiation wrapper for 'ram_16x2k'...Writing Verilog behavioral simulation model for 'ram_16x2k'...WARNING:sim - No files were found for the view xilinx_documentationGenerating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol.Generating metadata file...Generating ISE project file for 'ram_16x2k'...Generating ISE project...XCO file found: ram_16x2k.xcoXMDF file found: ram_16x2k_xmdf.tclAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.asy -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.ngc -view all -origin_type createdChecking file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.ngc" for project device match ...File"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.ngc" device information matches project device.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k.veo -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k_synth.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/ram_16x2k_synth.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.Top level has been set to "/ram_16x2k"Generating README file...Generating FLIST file...INFO:sim:948 - Finished FLIST file generation.Launching README viewer...Moving files to output directory...Finished moving files to output directorySaved CGP file for project 'coregen'.Saved CGP file for project 'coregen'.Closed project file.
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