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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.log] - Rev 202

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Welcome to Xilinx CORE Generator.
Help system initialized.
The IP Catalog has been reloaded.
Opening project file
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/coregen.cgp.
Recustomize and Generate (Under Original Project Settings)INFO:sim:172 - Generating IP...
Resolving generics for 'ram_16x8k_dp'...
Applying external generics to 'ram_16x8k_dp'...
Delivering associated files for 'ram_16x8k_dp'...
WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
   Verilog synthesis
Delivering EJava files for 'ram_16x8k_dp'...
Generating implementation netlist for 'ram_16x8k_dp'...
INFO:sim - Pre-processing HDL files for 'ram_16x8k_dp'...
Running synthesis for 'ram_16x8k_dp'
Running ngcbuild...
Writing VEO instantiation template for 'ram_16x8k_dp'...
Writing Verilog instantiation wrapper for 'ram_16x8k_dp'...
Writing Verilog behavioral simulation model for 'ram_16x8k_dp'...
WARNING:sim - No files were found for the view xilinx_documentation
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project file for 'ram_16x8k_dp'...
Generating ISE project...
XCO file found: ram_16x8k_dp.xco
XMDF file found: ram_16x8k_dp_xmdf.tcl
Adding
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/tmp/_cg/ram_16x8k_dp.asy -view all -origin_type imported
Adding
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/tmp/_cg/ram_16x8k_dp.ngc -view all -origin_type created
Checking file
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" for project device match ...
File
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" device information matches project
device.
Adding
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/tmp/_cg/ram_16x8k_dp.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
   verilog/coregen/tmp/_cg/ram_16x8k_dp.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/tmp/_cg/ram_16x8k_dp.veo -view all -origin_type imported
Adding
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
log/coregen/tmp/_cg/ram_16x8k_dp_synth.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
   verilog/coregen/tmp/_cg/ram_16x8k_dp_synth.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ram_16x8k_dp"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Closed project file.

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