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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 167
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window new WaveWindow -name "Waves for BMG Example Design"waveform using "Waves for BMG Example Design"waveform add -signals /ram_16x1k_dp_tb/statuswaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/CLKAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/ADDRAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/DINAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/WEAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/ENAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/DOUTAwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/CLKBwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/ADDRBwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/ENBwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/DINBwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/WEBwaveform add -signals /ram_16x1k_dp_tb/ram_16x1k_dp_synth_inst/bmg_port/DOUTBconsole submit -using simulator -wait no "run"