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/*******************************************************************************
*     This file is owned and controlled by Xilinx and must be used solely      *
*     for design, simulation, implementation and creation of design files      *
*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
*     devices or technologies is expressly prohibited and immediately          *
*     terminates your license.                                                 *
*                                                                              *
*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
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*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
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*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
*     All rights reserved.                                                     *
*******************************************************************************/

/*******************************************************************************
*     Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2       *
*                                                                              *
*     The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port     *
*     Block Memory and Single Port Block Memory LogiCOREs, but is not a        *
*     direct drop-in replacement.  It should be used in all new Xilinx         *
*     designs. The core supports RAM and ROM functions over a wide range of    *
*     widths and depths. Use this core to generate block memories with         *
*     symmetric or asymmetric read and write port widths, as well as cores     *
*     which can perform simultaneous write operations to separate              *
*     locations, and simultaneous read operations from the same location.      *
*     For more information on differences in interface and feature support     *
*     between this core and the Dual Port Block Memory and Single Port         *
*     Block Memory LogiCOREs, please consult the data sheet.                   *
*******************************************************************************/

// Interfaces:
//    CLK.ACLK
//        AXI4 Interconnect Clock Input
//    RST.ARESETN
//        AXI4 Interconnect Reset Input
//    AXI_SLAVE_S_AXI
//        AXI_SLAVE
//    AXILite_SLAVE_S_AXI
//        AXILite_SLAVE
//    BRAM_PORTA
//        BRAM_PORTA
//    BRAM_PORTB
//        BRAM_PORTB

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ram_16x1k_dp your_instance_name (
  .clka(clka), // input clka
  .ena(ena), // input ena
  .wea(wea), // input [1 : 0] wea
  .addra(addra), // input [9 : 0] addra
  .dina(dina), // input [15 : 0] dina
  .douta(douta), // output [15 : 0] douta
  .clkb(clkb), // input clkb
  .enb(enb), // input enb
  .web(web), // input [1 : 0] web
  .addrb(addrb), // input [9 : 0] addrb
  .dinb(dinb), // input [15 : 0] dinb
  .doutb(doutb) // output [15 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file ram_16x1k_dp.v when simulating
// the core, ram_16x1k_dp. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".