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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp.xise] - Rev 208
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xil_pn:valueState="default"/><property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/><property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/><property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/><property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ram_16x1k_dp_map.v" xil_pn:valueState="default"/><property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="ram_16x1k_dp_timesim.v" xil_pn:valueState="default"/><property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ram_16x1k_dp_synthesis.v" xil_pn:valueState="default"/><property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ram_16x1k_dp_translate.v" xil_pn:valueState="default"/><property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/><property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/><property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/><property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/><property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/><property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/><property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/><property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint 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xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/><property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/><property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/><property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/><property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/><property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/><property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/><property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/><property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/><property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/><property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/><property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/><property 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xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/><property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/><property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/><property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/><property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/><property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/><property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/><property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/><!-- --><!-- The following properties are for internal use only. These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="ram_16x1k_dp" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-28T21:29:29" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F844741F0AAF523029A8ABFF625423AB" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings/><libraries/><autoManagedFiles><!-- The following files are identified by `include statements in verilog --><!-- source files and are automatically managed by Project Navigator. --><!-- --><!-- Do not hand-edit this section, as it will be overwritten when the --><!-- project is analyzed based on files automatically identified as --><!-- include files. --></autoManagedFiles></project>
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