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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_sp/] [implement/] [implement.bat] - Rev 167
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rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy ram_16x1k_sp_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\ram_16x1k_sp.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\ram_16x1k_sp_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx9-csg324-2 ram_16x1k_sp_exdes
echo 'Running map'
map ram_16x1k_sp_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm ram_16x1k_sp_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v