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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_sp/] [implement/] [xst.prj] - Rev 167

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work ../example_design/ram_16x1k_sp_exdes.vhd

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