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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_sp.asy] - Rev 210
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Version 4SymbolType BLOCKTEXT 32 32 LEFT 4 ram_16x1k_spRECTANGLE Normal 32 32 544 1376LINE Wide 0 80 32 80PIN 0 80 LEFT 36PINATTR PinName addra[9:0]PINATTR Polarity INLINE Wide 0 112 32 112PIN 0 112 LEFT 36PINATTR PinName dina[15:0]PINATTR Polarity INLINE Normal 0 144 32 144PIN 0 144 LEFT 36PINATTR PinName enaPINATTR Polarity INLINE Wide 0 208 32 208PIN 0 208 LEFT 36PINATTR PinName wea[1:0]PINATTR Polarity INLINE Normal 0 272 32 272PIN 0 272 LEFT 36PINATTR PinName clkaPINATTR Polarity INLINE Wide 576 80 544 80PIN 576 80 RIGHT 36PINATTR PinName douta[15:0]PINATTR Polarity OUT
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