URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 167

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window new WaveWindow  -name  "Waves for BMG Example Design"
waveform  using  "Waves for BMG Example Design"


      waveform add -signals /ram_16x8k_dp_tb/status
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTA
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKB
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRB
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENB
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINB
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEB
      waveform add -signals /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTB
console submit -using simulator -wait no "run"

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 167